Processors Specifications
Pentium (P5) | ||||
---|---|---|---|---|
Intel Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
Pentium-60 (P5) March 22, 1993 - {$878} |
273 pins 60MHz (60x1.0) 5v |
Socket 4 | 8KB data (2-way) 8KB instruction (2-way) |
3.1 million 0.8µm process 296mm² die |
Pentium-66 (P5) March 22, 1993 - {$965} |
273 pins 66MHz (66x1.0) 5v |
Socket 4 | 8KB data (2-way) 8KB instruction (2-way) |
3.1 million 0.8µm process 296mm² die |
PentiumODP5V-120 (P5T) March 4, 1996 - {$399} |
273 pins 120MHz (60x2.0) 5v |
Socket 4 | 8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
PentiumODP5V-133 (P5T) March 4, 1996 - {$399} |
273 pins 133MHz (66x2.0) 5v |
Socket 4 | 8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
Pentium Classic (P54C) | ||||
---|---|---|---|---|
AMD Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
K5-PR75 (SSA5 - Model 0) March 27, 1996 - {$75} |
296 pins 75MHz (50x1.5) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.5µm process 271mm² die 0.35µm process 161mm² die |
K5-PR90 (SSA5 - Model 0) March 27, 1996 - {$99} |
296 pins 90MHz (60x1.5) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.35µm process 161mm² die |
K5-PR100 (SSA5 - Model 0) June 17, 1996 - {$84} |
296 pins 100MHz (66x1.5) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.35µm process 161mm² die |
K5-PR120 (5k86 - Model 1) October 7, 1996 - {$106} |
296 pins 90MHz (60x1.5) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.35µm process 181mm² die |
K5-PR133 (5k86 - Model 1) October 7, 1996 - {$134} |
296 pins 100MHz (66x1.5) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.35µm process 181mm² die |
K5-PR150 (5k86 - Model 2) January 13, 1997 |
296 pins 105MHz (60x1.75) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.35µm process 181mm² die |
K5-PR166 (5k86 - Model 2/3) January 13, 1997 |
296 pins 116MHz (66x1.75) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.35µm process 181mm² die |
K5-PR200 (5k86 - Model 3) 1Q 1997 |
296 pins 133MHz (66x2.0) 3.52v |
Socket 7 | 8KB data (4-way) 16KB instruction (4-way) |
4.3 million 0.35µm process 181mm² die |
Cyrix Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
6x86-PR90+ (M1) Manuf: SGS November 1995 |
296 pins 80MHz (40x2.0) 3.3v |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.65µm 3M process 394mm² die |
6x86-PR120+ (M1) Manuf: SGS October 9, 1995 - {$450} |
296 pins 100MHz (50x2.0) 3.3v |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.65µm 3M process 394mm² die |
6x86-PR133+ (M1R) Manuf: IBM February 5, 1996 - {$326} |
296 pins 110MHz (55x2.0) 3.3v |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.65µm 5M process 225mm² die |
6x86-PR150+ (M1R) Manuf: IBM February 5, 1996 - {$451} |
296 pins 120MHz (60x2.0) 3.3v or 3.52v |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.65µm 5M process 225mm² die |
6x86-PR166+ (M1R) Manuf: IBM February 5, 1996 - {$621} |
296 pins 133MHz (66x2.0) 3.3v or 3.52v |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.65µm 5M process 225mm² die |
6x86-PR200+ (M1R) Manuf: IBM June 3, 1996 - {$499} |
296 pins 150MHz (75x2.0) 3.52v |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.44µm 5M process ?mm² die |
6x86L-PR120+ (M1L) January 1997 |
296 pins 100MHz (50x2.0) 2.8v/3.3v split |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.35µm 5M process 169mm² die |
6x86L-PR133+ (M1L) February 1997 |
296 pins 110MHz (55x2.0) 2.8v/3.3v split |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.35µm 5M process 169mm² die |
6x86L-PR150+ (M1L) March 1997 |
296 pins 120MHz (60x2.0) 2.8v/3.3v split |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.35µm 5M process 169mm² die |
6x86L-PR166+ (M1L) April 1997 |
296 pins 133MHz (66x2.0) 2.8v/3.3v split |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.35µm 5M process 169mm² die |
6x86L-PR200+ (M1L) April 1997 |
296 pins 150MHz (75x2.0) 2.8v/3.3v split |
Socket 7 | 16KB unified (4-way) | 3.0 million 0.35µm 5M process 169mm² die |
Cx5gx86-120 (MediaGX) February 20, 1997 - {$79} |
352 pin BGA 120MHz (60x2.0) 3.3v |
Proprietary | 16KB unified | 2.4 million 0.6µm process 160mm² die |
Cx5gx86-133 (MediaGX) February 20, 1997 - {$99} |
352 pin BGA 133MHz (66x2.0) 3.3v |
Proprietary | 16KB unified | 2.4 million 0.6µm process 160mm² die |
Cx5gx86-150 (MediaGXi) June 6, 1997 - {$99} |
352 pin BGA 150MHz (60x2.5) 2.5v |
Proprietary | 16KB unified | 2.4 million 0.5µm process 160mm² die |
Cx5gx86-166 (MediaGXi) June 30, 1997 - {$88} |
352 pin BGA 166MHz (66x2.5) 2.5v |
Proprietary | 16KB unified | 2.4 million 0.5µm process 160mm² die |
Cx5gx86-180 (MediaGXi) June 30, 1997 - {$121} |
352 pin BGA 180MHz (60x3.0) 2.5v |
Proprietary | 16KB unified | 2.4 million 0.5µm process 160mm² die |
Intel Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
Pentium-75 (P54C) October 10, 1994 - {$535} |
296 pins 75MHz (50x1.5) MD,STD,VRT |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.2 million 0.6µm process 148mm² die |
Pentium-90 (P54C) March 7, 1994 - {$849} |
296 pins 90MHz (60x1.5) MD,STD,VR,VRT |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.2 million 0.6µm process 148mm² die |
Pentium-100 (P54C) March 7, 1994 - {$995} |
296 pins 100MHz (66x1.5) 100MHz (50x2.0) MD,STD,VR,VRE,VRT |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.2 million 0.6µm process 148mm² die |
Pentium-120 (P54CQS) March 27, 1995 - {$935} |
296 pins 120MHz (60x2.0) MD,STD,VRE,VRT |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
Pentium-133 (P54CS) June 12, 1995 - {$935} |
296 pins 133MHz (66x2.0) MD,STD,VRE,VRT |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
Pentium-150 (P54CS) January 4, 1996 - {$547} |
296 pins 150MHz (60x2.5) STD,VRT |
Socket 7 | 8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
Pentium-166 (P54CS) January 4, 1996 - {$749} |
296 pins 166MHz (66x2.5) VRE |
Socket 7 | 8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
Pentium-200 (P54CS) June 10, 1996 - {$599} |
296 pins 200MHz (66x3.0) VRE |
Socket 7 | 8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
PentiumODP3V-125 (P54CT) March 4, 1996 - {$399} |
320 pins 125MHz (50x2.5) 3.135v~3.600v |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
PentiumODP3V-150 (P54CT) May 1996 |
320 pins 150MHz (60x2.5) 3.135v~3.600v |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
PentiumODP3V-166 (P54CT) May 1996 |
320 pins 166MHz (66x2.5) 3.135v~3.600v |
Socket 5 Socket 7 |
8KB data (2-way) 8KB instruction (2-way) |
3.3 million 0.35µm process 90mm² die |
Pentium MMX (P55C) | ||||
---|---|---|---|---|
AMD Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
K6-166 MMX (Model 6) April 2, 1997 - {$244} |
321 pins 166MHz (66x2.5) 2.9v/3.3v split |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
8.8 million 0.35µm process 162mm² die |
K6-200 MMX (Model 6) April 2, 1997 - {$349} |
321 pins 200MHz (66x3.0) 2.9v/3.3v split |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
8.8 million 0.35µm process 162mm² die |
K6-233 MMX (Model 6) April 2, 1997 - {$469} |
321 pins 233MHz (66x3.5) 3.2v/3.3v split 3.3v/3.3v split |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
8.8 million 0.35µm process 162mm² die |
K6-233 MMX (Little Foot - Model 7) - mobile chip January 6, 1998 |
321 pins 233MHz (66x3.5) 2.2v/3.3v split |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
8.8 million 0.25µm process 68mm² die |
K6-266 MMX (Little Foot - Model 7) January 6, 1998 - {$268} |
321 pins 266MHz (66x4.0) 2.2v/3.3v split |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
8.8 million 0.25µm process 68mm² die |
K6-300 MMX (Little Foot - Model 7) April 7, 1998 - {$246} |
321 pins 300MHz (66x4.5) 2.2v/3.45v split |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
8.8 million 0.25µm process 68mm² die |
K6-2-266 MMX 3DNow! (Chompers - Model 8) May 28, 1998 - {$185} |
321 pins 266MHz (66x4.0) 2.2v/3.3v split |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-300 MMX 3DNow! (Chompers - Model 8) May 28, 1998 - {$281} |
321 pins 300MHz (100x3.0) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-333 MMX 3DNow! (Chompers - Model 8) May 28, 1998 - {$369} |
321 pins 333MHz (95x3.5) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-350 MMX 3DNow! (Chompers - Model 8) August 27, 1998 - {$317} |
321 pins 350MHz (100x3.5) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-300 MMX 3DNow! (Chompers - Model 8 CXT) November 16, 1998 |
321 pins 300MHz (100x3.0) 300MHz (66x4.5) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-333 MMX 3DNow! (Chompers - Model 8 CXT) November 16, 1998 |
321 pins 333MHz (95x3.5) 333MHz (66x5.0) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-350 MMX 3DNow! (Chompers - Model 8 CXT) November 16, 1998 |
321 pins 350MHz (100x3.5) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-366 MMX 3DNow! (Chompers - Model 8 CXT) November 16, 1998 - {$187} |
321 pins 366MHz (66x5.5) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-380 MMX 3DNow! (Chompers - Model 8 CXT) November 16, 1998 - {$213} |
321 pins 380MHz (95x4.0) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-400 MMX 3DNow! (Chompers - Model 8 CXT) November 16, 1998 - {$283} |
321 pins 400MHz (100x4.0) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-450 MMX 3DNow! (Chompers - Model 8 CXT) February 26, 1999 - {$203} |
321 pins 450MHz (100x4.5) 2.2v/3.3v split (Aug 99) 2.4v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-475 MMX 3DNow! (Chompers - Model 8 CXT) April 5, 1999 - {$213} |
321 pins 475MHz (95x5.5) 2.2v/3.3v split (Aug 99) 2.4v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-500 MMX 3DNow! (Chompers - Model 8 CXT) August 30, 1999 - {$167} |
321 pins 500MHz (100x5.0) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-533 MMX 3DNow! (Chompers - Model 8 CXT) November 29, 1999 - {$167} |
321 pins 533MHz (97x5.5) 2.2v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-2-550 MMX 3DNow! (Chompers - Model 8 CXT) February 22, 2000 - {$189} |
321 pins 550MHz (100x5.5) 2.3v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) |
9.3 million 0.25µm process 81mm² die |
K6-III-400 MMX 3DNow! (Sharptooth - Model 9) February 22, 1999 - {$284} |
321 pins 400MHz (100x4.0) 2.2v/3.3v split (Sep 99) 2.4v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
21.3 million 0.25µm process 118mm² die |
K6-III-450 MMX 3DNow! (Sharptooth - Model 9) February 22, 1999 - {$476} |
321 pins 450MHz (100x4.5) 2.2v/3.3v split (Sep 99) 2.4v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
21.3 million 0.25µm process 118mm² die |
K6-2+-450 MMX 3DNow! (?) - mobile chip April 18, 2000 - {$85} |
321 pins 450MHz (100x4.5) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
K6-2+-475 MMX 3DNow! (?) - mobile chip April 18, 2000 - {$98} |
321 pins 475MHz (95x5.0) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
K6-2+-500 MMX 3DNow! (?) - mobile chip April 18, 2000 - {$112} |
321 pins 500MHz (100x5.0) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
K6-2+-533 MMX 3DNow! (?) - mobile chip June 26, 2000 - {$85} |
321 pins 533MHz (97x5.5) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
K6-2+-550 MMX 3DNow! (?) - mobile chip June 26, 2000 - {$99} |
321 pins 550MHz (100x5.5) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
K6-III+-450 MMX 3DNow! (?) - mobile chip April 18, 2000 - {$140} |
321 pins 450MHz (100x4.5) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
K6-III+-475 MMX 3DNow! (?) - mobile chip April 18, 2000 - {$162} |
321 pins 475MHz (95x5.0) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
K6-III+-500 MMX 3DNow! (?) - mobile chip April 18, 2000 - {$184} |
321 pins 500MHz (100x5.0) 2.0v/3.3v split |
Super 7 | 32KB data (2-way) 32KB instruction (2-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
? million 0.18µm process ?mm² die |
Centaur (IDT) Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
IDT Winchip-150 MMX (C6) - not produced |
296 pins 150MHz (75x2.0) 3.3v |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
5.4 million 0.35µm process 88mm² die |
IDT Winchip-180 MMX (C6) October 13, 1997 - {$90} |
296 pins 180MHz (60x3.0) 3.3v or 3.52v |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
5.4 million 0.35µm process 88mm² die |
IDT Winchip-200 MMX (C6) October 13, 1997 - {$135} |
296 pins 200MHz (66x3.0) 3.3v or 3.52v |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
5.4 million 0.35µm process 88mm² die |
IDT Winchip-225 MMX (C6) December 1997 |
296 pins 225MHz (75x3.0) 3.52v |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
5.4 million 0.35µm process 88mm² die |
IDT Winchip-240 MMX (C6) December 1997 |
296 pins 240MHz (60x4.0) 3.52v |
Socket 7 | 32KB data (2-way) 32KB instruction (2-way) |
5.4 million 0.35µm process 88mm² die |
IDT Winchip-2-200 MMX 3DNow! (C6+) |
296 pins 200MHz (66x3.0) 3.3v or 3.52v |
Socket 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.25µm process 58mm² die |
IDT Winchip-2-225 MMX
3DNow! (C6+) October 13, 1998 |
296 pins 225MHz (75x3.0) 3.3v or 3.52v |
Socket 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.25µm process 58mm² die |
IDT Winchip-2-240 MMX
3DNow! (C6+) October 13, 1998 |
296 pins 240MHz (60x4.0) 3.3v or 3.52v |
Socket 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.25µm process 58mm² die |
IDT Winchip-2A-200 MMX 3DNow! (C6+) May 1999 |
296 pins 200MHz (66x3.0) 3.3v or 3.52v |
Socket 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.25µm process 58mm² die |
IDT Winchip-2A-233 MMX 3DNow! (C6+) May 1999 |
296 pins 233MHz (66x3.5) 3.3v or 3.52v |
Socket 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.25µm process 58mm² die |
IDT Winchip-2A-266 MMX 3DNow! (C6+) May 1999 |
296 pins 233MHz (100x2.33) 3.52v |
Socket 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.25µm process 58mm² die |
IDT Winchip-2B-200 MMX
3DNow! (C6+) [engineering sample only] |
296 pins 200MHz (66x3.0) 2.8v/3.3v split |
Super 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.18µm process 69mm² die |
(C6+) [not released] |
296 pins 200MHz (100x2.0) 2.8v/3.3v split |
Super 7 | 32KB data (4-way) 32KB instruction (2-way) |
6.0 million 0.18µm process 69mm² die |
IDT Winchip-3-233 MMX
3DNow! (C6-2L) [engineering sample only] |
296 pins 200MHz (66x3.0) 2.8v/3.3v split |
Socket 7 | 64KB data (4-way) 64KB instruction (2-way) |
10.2 million 0.25µm process 76mm² die |
(C6-2L) [not released] |
296 pins 233MHz (66x3.5) 2.8v/3.3v split |
Socket 7 | 64KB data (4-way) 64KB instruction (2-way) |
10.2 million 0.25µm process 76mm² die |
(C6-2L) [not released] |
296 pins 266MHz (66x4.0) 233MHz (100x2.33) 2.8v/3.3v split |
Socket 7 | 64KB data (4-way) 64KB instruction (2-way) |
10.2 million 0.25µm process 76mm² die |
(C6-2L) [not released] |
296 pins 266MHz (100x2.66) 250MHz (100x2.5) 2.8v/3.3v split |
Socket 7 | 64KB data (4-way) 64KB instruction (2-way) |
10.2 million 0.25µm process 76mm² die |
(C7) [not released] |
296 pins ?MHz (?x?) 2.8v/3.3v split |
Super 7 | 64KB data (4-way) 64KB instruction (2-way) |
11.6 million 0.25µm process 95mm² die |
(?) [not released] |
296 pins ?MHz (?x?) 1.8v/3.3v split |
Super 7 | 64KB data (4-way) 64KB instruction (2-way) |
11.6 million 0.18µm process 60mm² die |
Cyrix Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
Cx5gx86-200 MMX (MediaGXm) January 6, 1998 - {$114} |
352 pin BGA 320 pin SPGA 200MHz (66x3.0) 2.5v |
Proprietary | 16KB unified | 2.4 million 0.5µm process 160mm² die |
Cx5gx86-233 MMX (MediaGXm) March 18, 1998 - {$81} |
320 pin SPGA 233MHz (66x3.5) 2.5v |
Proprietary | 16KB unified | 2.4 million 0.5µm process 160mm² die |
Cx5gx86-266 MMX (MediaGXm) October 1998 |
320 pin SPGA 266MHz (66x4.0) 2.5v |
Proprietary | 16KB unified | 2.4 million 0.5µm process 160mm² die |
6x86MX-PR166 MMX (M2) Manuf: IBM May 30, 1997 - {$190} |
296 pins 150MHz (60x2.5) 133MHz (66x2.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm 5M process 197mm² die |
6x86MX-PR200 MMX (M2) Manuf: IBM (0.35µ) Manuf: NSI (0.30µ) May 30, 1997 - {$240} |
296 pins 166MHz (66x2.5) 150MHz (75x2.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm 5M process 197mm² die 0.30µm process (2Q 98) 156mm² die |
6x86MX-PR233 MMX (M2) Manuf: IBM (0.35µ) Manuf: NSI (0.30µ) May 30, 1997 - {$320} |
296 pins 200MHz (66x3.0) 188MHz (75x2.5) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm 5M process 197mm² die 0.30µm process (2Q 98) 156mm² die |
6x86MX-PR266 MMX (M2) - Very few chips produced. Manuf: IBM (0.35µ) Manuf: NSI (0.30µ) March 19, 1998 - {$180} |
296 pins 208MHz (83x2.5) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm 5M process 197mm² die 0.30µm process (2Q 98) 156mm² die |
M II-233 MMX (M2) Manuf: NSI |
296 pins 200MHz (66x3.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.30µm process 156mm² die |
M II-266 MMX (M2) Manuf: NSI |
296 pins 200MHz (66x3.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.25µm process 88mm² die |
M II-300 MMX (M2) Manuf: NSI April 14, 1998 - {$180} |
296 pins 233MHz (66x3.5) 225MHz (75x3.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.30µm process 156mm² die 0.25µm process (1Q 99) 88mm² die |
M II-333 MMX (M2) Manuf: NSI June 15, 1998 - {$180} |
296 pins 250MHz (100x2.5) 2.9v/3.3v split |
Super 7 | 64KB unified (4-way) | 6.0 million 0.30µm process 156mm² die 0.25µm process (1Q 99) 88mm² die |
M II-333 MMX (M2) Manuf: NSI March 1999 |
296 pins 250MHz (83x3.0) 2.9v/3.3v split |
Super 7 | 64KB unified (4-way) | 6.0 million 0.25µm process 88mm² die |
M II-366 MMX (M2) Manuf: NSI March 1999 |
296 pins 250MHz (100x2.5) 2.9v/3.3v split |
Super 7 | 64KB unified (4-way) | 6.0 million 0.25µm process 88mm² die |
M II-400 MMX (M2) Manuf: NSI June 1999 |
321 pins 285MHz (95x3.0) 2.2v/3.3v split |
Super 7 | 64KB unified (4-way) | 6.0 million 0.18µm process 65mm² die |
M II-433 MMX (M2) Manuf: NSI June 1999 |
321 pins 300MHz (100x3.0) 2.2v/3.3v split |
Super 7 | 64KB unified (4-way) | 6.0 million 0.18µm process 65mm² die |
IBM Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
6x86MX-PR166 MMX (M2) May 30, 1997 - {$202} |
296 pins 150MHz (60x2.5) 133MHz (66x2.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm process 197mm² die |
6x86MX-PR200 MMX (M2) May 30, 1997 - {$369} |
296 pins 166MHz (66x2.5) 150MHz (75x2.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm process 197mm² die 0.30µm process (2Q 98) ?mm² die |
6x86MX-PR233 MMX (M2) May 30, 1997 - {$477} |
296 pins 200MHz (66x3.0) 188MHz (75x2.5) 166MHz (83x2.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm process 197mm² die 0.30µm process (2Q 98) ?mm² die |
6x86MX-PR266 MMX (M2) - Very few chips produced. March 19, 1998 |
296 pins 208MHz (83x2.5) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.35µm process 197mm² die 0.30µm process (2Q 98) ?mm² die |
6x86MX-PR300 MMX (M2) May 19, 1998 - {$217} |
296 pins 233MHz (66x3.5) 225MHz (75x3.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.25µm process 119mm² die |
6x86MX-PR333 MMX (M2) May 19, 1998 - {$299} |
296 pins 263MHz (75x3.5) 250MHz (83x3.0) 2.9v/3.3v split |
Socket 7 | 64KB unified (4-way) | 6.0 million 0.25µm process 119mm² die |
Intel Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
Pentium-166 MMX (P55C) January 8, 1997 - {$407} |
296 pins 166MHz (66x2.5) 2.8v/3.3v split |
Socket 7 | 16KB data (4-way) 16KB instruction (4-way) |
4.5 million 0.35µm process 141mm² die |
Pentium-200 MMX (P55C) January 8, 1997 - {$550} |
296 pins 200MHz (66x3.0) 2.8v/3.3v split |
Socket 7 | 16KB data (4-way) 16KB instruction (4-way) |
4.5 million 0.35µm process 141mm² die |
Pentium-233 MMX (P55C) June 2, 1997 - {$594} |
296 pins 233MHz (66x3.5) 2.8v/3.3v split |
Socket 7 | 16KB data (4-way) 16KB instruction (4-way) |
4.5 million 0.35µm process 141mm² die |
PentiumODPMT-150 MMX (P54CTB) March 3, 1997 - {$399} |
320 pins 150MHz (60x2.5) 125MHz (50x2.5) 3.3v to 2.8v |
Socket 5 Socket 7 |
16KB data (4-way) 16KB instruction (4-way) |
4.5 million 0.35µm process 141mm² die |
PentiumODPMT-166 MMX (P54CTB) March 3, 1997 - {$499} |
320 pins 166MHz (66x2.5) 3.3v to 2.8v |
Socket 5 Socket 7 |
16KB data (4-way) 16KB instruction (4-way) |
4.5 million 0.35µm process 141mm² die |
PentiumODPMT-180 MMX (P54CTB) August 4, 1997 - {$299} |
320 pins 180MHz (60x3.0) 3.3v to 2.8v |
Socket 5 Socket 7 |
16KB data (4-way) 16KB instruction (4-way) |
4.5 million 0.35µm process 141mm² die |
PentiumODPMT-200 MMX (P54CTB) August 4, 1997 - {$349} |
320 pins 200MHz (66x3.0) 3.3v to 2.8v |
Socket 7 | 16KB data (4-way) 16KB instruction (4-way) |
4.5 million 0.35µm process 141mm² die |
Rise Processors |
Natural State |
Sockets | L1 Cache (Associativity) |
Transistors |
mP6-166 MMX (?) February 1999 - {$50} |
296 pins 166MHz (83x2.0) 2.8v/3.3v split |
Socket 7 | 8KB data 8KB instruction |
3.6 million 0.25µm process 107mm² die |
mP6-233 MMX (?) February 1999 - {$60} |
296 pins 190MHz (95x2.0) 2.8v/3.3v split |
Super 7 | 8KB data 8KB instruction |
3.6 million 0.25µm process 107mm² die |
mP6-266 MMX (?) February 1999 - {$70} |
296 pins 200MHz (100x2.0) 2.8v/3.3v split |
Super 7 | 8KB data 8KB instruction |
3.6 million 0.25µm process 107mm² die |
(?) [not released] |
296 pins 250MHz (100x2.5) 2.8v/3.3v split |
Super 7 | 8KB data (2-way) 8KB instruction (2-way) 256KB on-Die L2 (1-way) ? cacheable |
18 million 0.25µm process ?mm² die |
(?) [not released] |
296 pins 285MHz (95x3.0) 2.0v/3.3v split |
Super 7 | 8KB data (2-way) 8KB instruction (2-way) 256KB on-Die L2 (1-way) ? cacheable |
18 million 0.18µm process 105mm² die |
(?) [not released] |
296 pins 300MHz (100x3.0) 2.0v/3.3v split |
Super 7 | 8KB data (2-way) 8KB instruction (2-way) 256KB on-Die L2 (1-way) ? cacheable |
18 million 0.18µm process 105mm² die |
(?) [not released] |
296 pins 350MHz (100x3.5) 2.0v/3.3v split |
Super 7 | 8KB data (2-way) 8KB instruction (2-way) 256KB on-Die L2 (1-way) ? cacheable |
18 million 0.18µm process 105mm² die |
Pentium Pro (P6) | ||||
---|---|---|---|---|
Intel Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Pentium Pro-133 (P6) [engineering sample only] |
387 pins 133MHz (66x2.0) 3.1v |
Socket 8 | 8KB data (2-way) 8KB instruction (4-way) 256KB on-Chip unified L2 (4-way) * 64GB cacheable |
5.5 million 0.6µm process 306mm² die 15.5 million L2 {0.6µm - 202mm²} |
Pentium Pro-150 (P6) November 1, 1995 - {$974} |
387 pins 150MHz (60x2.5) 3.1v |
Socket 8 | 8KB data (2-way) 8KB instruction (4-way) 256KB on-Chip unified L2 (4-way) * 64GB cacheable |
5.5 million 0.6µm process 306mm² die 15.5 million L2 {0.6µm - 202mm²} |
Pentium Pro-166 (P6) November 1, 1995 - {$1682} |
387 pins 166MHz (66x2.5) 3.3v |
Socket 8 | 8KB data (2-way) 8KB instruction (4-way) 512KB on-Chip unified L2 (4-way) * 64GB cacheable |
5.5 million 0.35µm process 195mm² die 31 million L2 {0.35µm - 242mm²} |
Pentium Pro-180 (P6) November 1, 1995 - {$1075} |
387 pins 180MHz (60x3.0) 3.3v |
Socket 8 | 8KB data (2-way) 8KB instruction (4-way) 256KB on-Chip unified L2 (4-way) * 64GB cacheable |
5.5 million 0.35µm process 195mm² die 15.5 million L2 {0.6µm - 202mm²} |
Pentium Pro-200 (P6) November 1, 1995 - {$1325} (256KB) November 1, 1995 - {$1989} (512KB) August 18, 1997 - {$2650} (1MB) |
387 pins 200MHz (66x3.0) 3.3v or 3.5v |
Socket 8 | 8KB data (2-way) 8KB instruction (4-way) 256KB or 512KB or 1MB on-Chip unified L2 (4-way) * 64GB cacheable |
5.5 million 0.35µm process 195mm² die 15.5 million L2 {0.6µm - 202mm²} (256KB) 31 million L2 {0.35µm - 242mm²} (512KB) 62 million L2 {0.35µm - (2) 242mm²} (1MB) |
Pentium II OverDrive-333 MMX (P6T) August 10, 1998 - {$599} |
387 pins 300MHz (60x5.0) 333MHz (66x5.0) 2.0v/2.5v/3.3v split |
Socket 8 | 16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (4-way) * 64GB cacheable |
? million 0.25µm process ?mm² die |
Pentium II (Slot 1) | ||||
---|---|---|---|---|
Intel Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Pentium II-233 MMX (Klamath) May 7, 1997 - {$636} |
528 pins (242 pin SEC) 233MHz (66x3.5) 2.8v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 512MB cacheable |
7.5 million 0.35µm process 203mm² die |
Pentium II-266 MMX (Klamath) May 7, 1997 - {$775} |
528 pins (242 pin SEC) 266MHz (66x4.0) 2.8v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 512MB cacheable |
7.5 million 0.35µm process 203mm² die |
Pentium II-300 MMX (Klamath) May 7, 1997 - {$1981} |
528 pins (242 pin SEC) 300MHz (66x4.5) 2.8v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 512MB cacheable |
7.5 million 0.35µm process 203mm² die |
Pentium II-266 MMX (Deschutes) September 1, 1998 - {$159} |
528 pins (242 pin SEC) 266MHz (66x4.0) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
7.5 million 0.25µm process 131mm² die 118mm² die (Aug 98) |
Pentium II-300 MMX (Deschutes) September 1, 1998 - {$192} |
528 pins (242 pin SEC) 300MHz (66x4.5) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
7.5 million 0.25µm process 131mm² die 118mm² die (Aug 98) |
Pentium II-333 MMX (Deschutes) January 26, 1998 - {$722} |
528 pins (242 pin SEC) 333MHz (66x5.0) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * dA0 512MB cacheable * dA1 4GB cacheable * dB0 4GB cacheable |
7.5 million 0.25µm process 131mm² die 118mm² die (Aug 98) |
Pentium II-350 MMX (Deschutes) April 15, 1998 - {$621} |
528 pins (242 pin SEC) 350MHz (100x3.5) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
7.5 million 0.25µm process 131mm² die 118mm² die (Aug 98) |
Pentium II-400 MMX (Deschutes) April 15, 1998 - {$824} |
528 pins (242 pin SEC) 400MHz (100x4.0) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
7.5 million 0.25µm process 131mm² die 118mm² die (Aug 98) |
Pentium II-450 MMX (Deschutes) August 24, 1998 - {$669} |
528 pins (242 pin SEC) 450MHz (100x4.5) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
7.5 million 0.25µm process 118mm² die |
Pentium III-450 MMX SSE (Katmai) February 26, 1999 - {$496} |
570 pins (242 pin SEC) 450MHz (100x4.5) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III-500 MMX SSE (Katmai) February 26, 1999 - {$696} |
570 pins (242 pin SEC) 500MHz (100x5.0) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III-533B MMX
SSE (Katmai) September 27, 1999 - {$369} |
570 pins (242 pin SEC) 533MHz (133x4.0) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III-550 MMX SSE (Katmai) May 17, 1999 - {$744} |
570 pins (242 pin SEC) 550MHz (100x5.5) 2.0v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III-600 MMX SSE (Katmai) August 2, 1999 - {$669} |
570 pins (242 pin SEC) 600MHz (100x6.0) 2.05v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III-600B MMX
SSE (Katmai) September 27, 1999 - {$615} |
570 pins (242 pin SEC) 600MHz (133x4.5) 2.05v/3.3v split |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (1/2 speed) (4-way) * 4GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III-533EB MMX
SSE (Coppermine) October 25, 1999 - {$305} |
495 pins (242 pin SEC) 533MHz (133x4.0) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) |
Pentium III-550E MMX
SSE (Coppermine) March 1, 2000 |
495 pins (242 pin SEC) 550MHz (100x5.5) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) |
Pentium III-600E MMX
SSE (Coppermine) October 25, 1999 - {$455} |
495 pins (242 pin SEC) 600MHz (100x6.0) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-600EB MMX
SSE (Coppermine) October 25, 1999 - {$455} |
495 pins (242 pin SEC) 600MHz (133x4.5) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-650 MMX
SSE (Coppermine) October 25, 1999 - {$583} |
495 pins (242 pin SEC) 650MHz (100x6.5) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-667 MMX
SSE (Coppermine) October 25, 1999 - {$605} |
495 pins (242 pin SEC) 666MHz (133x5.0) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-700 MMX
SSE (Coppermine) October 25, 1999 - {$754} |
495 pins (242 pin SEC) 700MHz (100x7.0) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-733 MMX
SSE (Coppermine) October 25, 1999 - {$776} |
495 pins (242 pin SEC) 733MHz (133x5.5) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-750 MMX
SSE (Coppermine) December 20, 1999 - {$803} |
495 pins (242 pin SEC) 750MHz (100x7.5) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-800 MMX
SSE (Coppermine) December 20, 1999 - {$851} |
495 pins (242 pin SEC) 800MHz (100x8.0) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-800EB MMX
SSE (Coppermine) December 20, 1999 - {$851} |
495 pins (242 pin SEC) 800MHz (133x6.0) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-850 MMX
SSE (Coppermine) March 20, 2000 - {$765} |
495 pins (242 pin SEC) 850MHz (100x8.5) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jul 00) |
Pentium III-866 MMX
SSE (Coppermine) March 20, 2000 - {$776} |
495 pins (242 pin SEC) 866MHz (133x6.5) 1.65v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jul 00) |
Pentium III-933 MMX SSE (Coppermine) May 24, 2000 - {$744} |
495 pins (242 pin SEC) 933MHz (133x7.0) 1.7v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jul 00) |
Pentium III-1.0B MMX
SSE (Coppermine) March 8, 2000 - {$990} |
495 pins (242 pin SEC) 1000MHz (133x7.5) 1.7v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jul 00) |
Pentium III-1.0G MMX
SSE (Coppermine) July 31, 2000 |
495 pins (242 pin SEC) 1000MHz (100x10.0) 1.7v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die |
Pentium III-1.13G MMX
SSE (Coppermine) July 31, 2000 - {$990} [recalled in Aug] |
495 pins (242 pin SEC) 1133MHz (133x8.5) 1.8v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die |
Celeron-266 MMX (Covington) April 15, 1998 - {$155} |
528 pins (242 pin SEPP) 266MHz (66x4.0) 2.0v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) |
7.5 million 0.25µm process 131mm² die |
Celeron-300 MMX (Covington) June 8, 1998 - {$159} |
528 pins (242 pin SEPP) 300MHz (66x4.5) 2.0v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) |
7.5 million 0.25µm process 131mm² die |
Celeron-300A MMX (Mendocino) August 24, 1998 - {$149} |
528 pins (242 pin SEPP) 300MHz (66x4.5) 2.0v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-333 MMX (Mendocino) August 24, 1998 - {$192} |
528 pins (242 pin SEPP) 333MHz (66x5.0) 2.0v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-366 MMX (Mendocino) January 4, 1999 - {$131} |
528 pins (242 pin SEPP) 366MHz (66x5.5) 2.0v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-400 MMX (Mendocino) January 4, 1999 - {$166} |
528 pins (242 pin SEPP) 400MHz (66x6.0) 2.0v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-433 MMX (Mendocino) March 22, 1999 - {$177} |
528 pins (242 pin SEPP) 433MHz (66x6.5) 2.0v |
Slot 1 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Pentium II/III Xeon (Slot 2) | ||||
---|---|---|---|---|
Intel Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Pentium II Xeon-400 MMX (Drake) June 29, 1998 - {$1124} (512KB) June 29, 1998 - {$2836} (1MB) |
528 pins (330 pin SEC) 400MHz (100x4.0) 2.0v/2.5v split |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 512KB or 1MB unified L2 (4-way) * 64GB cacheable |
7.5 million 0.25µm process 131mm² die 118mm² die (Aug 98) |
Pentium II Xeon-450 MMX (Drake) October 6, 1998 - {$824} (512KB) January 5, 1999 - {$1980} (1MB) January 5, 1999 - {$3692} (2MB) |
528 pins (330 pin SEC) 450MHz (100x4.5) 2.0v/2.7v split |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 512KB or 1MB or 2MB unified L2 (4-way) * 64GB cacheable |
7.5 million 0.25µm process 118mm² die |
Pentium III Xeon-500 MMX
SSE (Tanner) March 17, 1999 - {$931} (512KB) March 17, 1999 - {$1980} (1MB) March 17, 1999 - {$3692} (2MB) |
570 pins (330 pin SEC) 500MHz (100x5.0) 2.0v/2.7v split 2.0v/2.0v split (2MB L2) |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 512KB or 1MB or 2MB unified L2 (4-way) * 64GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III Xeon-550 MMX SSE (Tanner - 2-way) April 7, 1999 - {$1059} |
570 pins (330 pin SEC) 550MHz (100x5.5) 2.0v/2.0v split |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 512KB unified L2 (4-way) * 64GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III Xeon-550 MMX
SSE (Tanner) August 23, 1999 - {$931} (512KB) August 23, 1999 - {$1980} (1MB) August 23, 1999 - {$3692} (2MB) |
570 pins (330 pin SEC) 550MHz (100x5.5) 2.0v/2.0v split |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 512KB or 1MB or 2MB unified L2 (4-way) * 64GB cacheable |
9.5 million 0.25µm process 123mm² die |
Pentium III Xeon-600 MMX
SSE (Cascades) October 25, 1999 - {$505} |
495 pins (330 pin SEC) 600MHz (133x4.5) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) |
Pentium III Xeon-667 MMX
SSE (Cascades) October 25, 1999 - {$655} |
495 pins (330 pin SEC) 666MHz (133x5.0) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) |
Pentium III Xeon-700 MMX
SSE (Cascades) May 22, 2000 (1MB) - {$1177} May 22, 2000 (2MB) - {$1980} |
495 pins (330 pin SEC) 700MHz (100x7.0) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 1MB or 2MB on-Die unified L2 (8-way) * 64GB cacheable |
140 million 0.18µm process 300+mm² die |
Pentium III Xeon-733 MMX
SSE (Cascades) October 25, 1999 - {$826} |
495 pins (330 pin SEC) 733MHz (133x5.5) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 100mm² die (Jul 00) |
Pentium III Xeon-800 MMX
SSE (Cascades) January 12, 2000 - {$901} |
495 pins (330 pin SEC) 800MHz (133x6.0) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 100mm² die (Jul 00) |
Pentium III Xeon-866 MMX
SSE (Cascades) March 13, 2000 |
495 pins (330 pin SEC) 866MHz (133x6.5) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
28 million 0.18µm process 105mm² die 100mm² die (Jul 00) |
Pentium III Xeon-900 MMX
SSE (Cascades) March 20, 2001 - {$3692} |
495 pins (330 pin SEC) 900MHz (100x9.0) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 2MB on-Die unified L2 (8-way) * 64GB cacheable |
140 million 0.18µm process 300+mm² die |
Pentium III Xeon-933 MMX
SSE (Cascades) May 24, 2000 - {$794} |
495 pins (330 pin SEC) 933MHz (133x7.0) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
28 million 0.18µm process 105mm² die 100mm² die (Jul 00) |
Pentium III Xeon-1G MMX
SSE (Cascades) August 22, 2000 - {$719} |
495 pins (330 pin SEC) 1000MHz (133x7.5) 2.8v or 5.0v or 12.0v |
Slot 2 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
28 million 0.18µm process 100mm² die |
Socket 370 | ||||
---|---|---|---|---|
Cyrix Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
(Mojave) [not released] |
370 pins ?MHz (133x?) 1.8v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 256KB on-Die L2 (8-way) * ?GB cacheable |
25 million 0.21µm process 110mm² die |
Intel Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Celeron-300A MMX (Mendocino) November 30, 1998 - {$70} |
370 pins 300MHz (66x4.5) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-333 MMX (Mendocino) November 30, 1998 - {$87} |
370 pins 333MHz (66x5.0) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-366 MMX (Mendocino) January 4, 1999 - {$123} |
370 pins 366MHz (66x5.5) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-400 MMX (Mendocino) January 4, 1999 - {$158} |
370 pins 400MHz (66x6.0) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-433 MMX (Mendocino) March 22, 1999 - {$169} |
370 pins 433MHz (66x6.5) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-466 MMX (Mendocino) April 26, 1999 - {$169} |
370 pins 466MHz (66x7.0) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-500 MMX (Mendocino) August 2, 1999 - {$167} |
370 pins 500MHz (66x7.5) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
Celeron-533 MMX (Mendocino) January 4, 2000 - {$167} |
370 pins 533MHz (66x8.0) 2.0v |
Socket 370 | 16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
19 million 0.25µm process 154mm² die |
(Coppermine-128) March 29, 2000 [may not exist] |
370 pins 500MHz (66x7.5) 1.5v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die |
Celeron-533A MMX
SSE (Coppermine-128) March 29, 2000 |
370 pins 533MHz (66x8.0) 1.5v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jun 00) |
Celeron-566 MMX
SSE (Coppermine-128) March 29, 2000 - {$167} |
370 pins 566MHz (66x8.5) 1.5v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jun 00) |
Celeron-600 MMX
SSE (Coppermine-128) March 29, 2000 - {$181} |
370 pins 600MHz (66x9.0) 1.5v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jun 00) |
Celeron-633 MMX SSE (Coppermine-128) June 26, 2000 - {$138} |
370 pins 633MHz (66x9.5) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jun 00) |
Celeron-667 MMX SSE (Coppermine-128) June 26, 2000 - {$170} |
370 pins 666MHz (66x10.0) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jun 00) |
Celeron-700 MMX SSE (Coppermine-128) June 26, 2000 - {$192} |
370 pins 700MHz (66x10.5) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jun 00) |
Celeron-733 MMX
SSE (Coppermine-128) November 13, 2000 - {$112} |
370 pins 733MHz (66x11.0) 1.65v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die 95mm² die (Jul 01) |
Celeron-766 MMX
SSE (Coppermine-128) November 13, 2000 - {$170} |
370 pins 766MHz (66x11.5) 1.65v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die |
Celeron-800 MMX
SSE (Coppermine-128) January 3, 2001 - {$170} |
370 pins 800MHz (100x8.0) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die 95mm² die (Jul 01) |
Celeron-850 MMX
SSE (Coppermine-128) April 9, 2001 - {$138} |
370 pins 850MHz (100x8.5) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die 95mm² die (Jul 01) |
Celeron-900 MMX SSE (Coppermine-128) July 2, 2001 - {$103} |
370 pins 900MHz (100x9.0) 1.75v |
Socket
370 (FC-PGA) (FC-PGA2) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Celeron-950 MMX
SSE (Coppermine-128) August 31, 2001 - {$74} |
370 pins 950MHz (100x9.5) 1.75v |
Socket
370 (FC-PGA) (FC-PGA2) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Celeron-1.0G MMX
SSE (Coppermine-128) August 31, 2001 - {$89} |
370 pins 1000MHz (100x10.0) 1.75v |
Socket
370 (FC-PGA) (FC-PGA2) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Celeron-1.1G MMX
SSE (Coppermine-128) August 31, 2001 - {$103} |
370 pins 1100MHz (100x11.0) 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 128KB on-Die unified L2 (4-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Celeron-900A MMX SSE (Tualatin) May 15, 2002 |
370 pins 900MHz (100x9.0) 1.475v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
44 million 0.13µm process 80mm² die |
Celeron-1.0A MMX SSE (Tualatin) January 3, 2002 |
370 pins 1000MHz (100x10.0) 1.475v or 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
44 million 0.13µm process 80mm² die |
Celeron-1.1A MMX SSE (Tualatin) January 3, 2002 |
370 pins 1100MHz (100x11.0) 1.475v or 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
44 million 0.13µm process 80mm² die |
Celeron-1.2G MMX SSE (Tualatin) October 2, 2001 - {$103} |
370 pins 1200MHz (100x12.0) 1.475v or 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
44 million 0.13µm process 80mm² die |
Celeron-1.3G MMX SSE (Tualatin) January 3, 2002 - {$118} |
370 pins 1300MHz (100x13.0) 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
44 million 0.13µm process 80mm² die |
Celeron-1.4G MMX SSE (Tualatin) May 15, 2002 - {$89} |
370 pins 1400MHz (100x14.0) 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-500E MMX
SSE (Coppermine) October 25, 1999 - {$239} |
370 pins 500MHz (100x5.0) 1.6v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) |
Pentium III-533EB MMX
SSE (Coppermine) March 1, 2000 |
370 pins 533MHz (133x4.0) 1.65v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) |
Pentium III-550E MMX
SSE (Coppermine) October 25, 1999 - {$368} |
370 pins 550MHz (100x5.5) 1.6v or 1.65v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-600E MMX
SSE (Coppermine) March 1, 2000 |
370 pins 600MHz (100x6.0) 1.65v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) 95mm² die (May 01) |
Pentium III-600EB MMX
SSE (Coppermine) March 1, 2000 |
370 pins 600MHz (133x4.5) 1.65v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-650 MMX
SSE (Coppermine) March 1, 2000 |
370 pins 650MHz (100x6.5) 1.65v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-667 MMX
SSE (Coppermine) March 1, 2000 |
370 pins 666MHz (133x5.0) 1.65v or 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-700 MMX
SSE (Coppermine) March 1, 2000 |
370 pins 700MHz (100x7.0) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) 95mm² die (May 01) |
Pentium III-733 MMX
SSE (Coppermine) March 1, 2000 |
370 pins 733MHz (133x5.5) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-750 MMX
SSE (Coppermine) March 1, 2000 |
370 pins 750MHz (100x7.5) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) 95mm² die (May 01) |
Pentium III-800E MMX
SSE (Coppermine) March 1, 2000 |
370 pins 800MHz (100x8.0) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) |
Pentium III-800EB MMX
SSE (Coppermine) March 1, 2000 |
370 pins 800MHz (133x6.0) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 106mm² die 105mm² die (Mar 00) 90mm² die (Jul 00) 95mm² die (May 01) |
Pentium III-850 MMX
SSE (Coppermine) March 20, 2000 - {$765} |
370 pins 850MHz (100x8.5) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jul 00) |
Pentium III-866 MMX
SSE (Coppermine) March 20, 2000 - {$776} |
370 pins 866MHz (133x6.5) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) (FC-PGA2) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jul 00) 95mm² die (May 01) |
Pentium III-900 MMX
SSE (Coppermine) October, 2000 |
370 pins 900MHz (100x9.0) 1.7v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die 95mm² die (May 01) |
Pentium III-933 MMX SSE (Coppermine) May 24, 2000 - {$744} |
370 pins 933MHz (133x7.0) 1.65v or 1.7v or 1.75v |
Socket
370 (FC-PGA) (FC-PGA2) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 105mm² die 90mm² die (Jul 00) 95mm² die (May 01) |
Pentium III-1.0G MMX
SSE (Coppermine) June, 2001 |
370 pins 1000MHz (100x10.0) 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Pentium III-1.0B MMX
SSE (Coppermine) January, 2001 |
370 pins 1000MHz (133x7.5) 1.7v or 1.75v or 1.76v |
Socket
370 (FC-PGA) (FC-PGA2) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 90mm² die 95mm² die (May 01) |
Pentium III-1.1G MMX
SSE (Coppermine) June, 2001 |
370 pins 1100MHz (100x11.0) 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Pentium III-1.13G MMX
SSE (Coppermine) June, 2001 |
370 pins 1133MHz (133x8.5) 1.75v |
Socket
370 (FC-PGA) |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Pentium III-866 MMX
SSE (Coppermine-T) June, 2001 |
370 pins 866MHz (133x6.5) 1.75v |
Socket 370 (FC-PGA) 1.5v AGTL+ 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Pentium III-933 MMX
SSE (Coppermine-T) June, 2001 |
370 pins 933MHz (133x7.0) 1.75v |
Socket 370 (FC-PGA) 1.5v AGTL+ 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Pentium III-1.0B MMX
SSE (Coppermine-T) June, 2001 |
370 pins 1000MHz (133x7.5) 1.75v |
Socket 370 (FC-PGA2) 1.5v AGTL+ 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Pentium III-1.13G MMX
SSE (Coppermine-T) June, 2001 |
370 pins 1133MHz (133x8.5) 1.75v |
Socket 370 (FC-PGA2) 1.5v AGTL+ 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
28 million 0.18µm process 95mm² die |
Pentium III-1.0B MMX SSE (Tualatin) July 18, 2001 |
370 pins 1000MHz (133x7.5) 1.475v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-1.13A MMX
SSE (Tualatin) July, 2001 |
370 pins 1133MHz (133x8.5) 1.475v or 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-1.2G MMX SSE (Tualatin) July, 2001 |
370 pins 1200MHz (133x9.0) 1.475v or 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-1.33G MMX
SSE (Tualatin) December, 2001 |
370 pins 1333MHz (133x10.0) 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-1.4G MMX SSE (Tualatin) June, 2002 |
370 pins 1400MHz (133x10.5) 1.5v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 256KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-700 MMX
SSE (Tualatin) November 13, 2001 |
370 pins 700MHz (100x7.0) 1.1v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-800 MMX
SSE (Tualatin) March 19, 2002 |
479 balls 800MHz (133x6.0) 1.15v |
Proprietary µFCBGA 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-900 MMX
SSE (Tualatin) 3Q 2002? |
370 pins 900MHz (100x9.0) ?v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-933 MMX
SSE (Tualatin) 3Q 2002? |
370 pins 933MHz (133x7.0) 1.1v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-1.13G MMX
SSE (Tualatin) June 21, 2001 |
370 pins 1133MHz (133x8.5) 1.45v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-1.26G MMX
SSE (Tualatin) July 18, 2001 |
370 pins 1266MHz (133x9.5) 1.45v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-1.4G MMX
SSE (Tualatin) January 8, 2002 - {$315} |
370 pins 1400MHz (133x10.5) 1.45v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Pentium III-S-1.53G MMX
SSE (Tualatin) 3Q 2002? |
370 pins 1533MHz (133x11.5) 1.45v |
Socket 370 (FC-PGA2) 1.25v AGTL |
16KB data (4-way) 16KB instruction (4-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
44 million 0.13µm process 80mm² die |
Rise Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
(Tiger) [not released] |
370 pins ?MHz (100x?) 1.8v/2.5v split |
Socket 370 | ?KB data ?KB instruction ?KB on-Die L2 ? cacheable |
? million 0.18µm process ?mm² die |
VIA Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
(Joshua) February 22, 2000 [not released] |
370 pins 333MHz (66x5.0) 2.2v |
Socket 370 | 64KB unified (4-way) 256KB on-Die L2 (8-way exclusive) * 4GB cacheable |
22 million 0.18µm process ?mm² die |
(Joshua) February 22, 2000 [not released] |
370 pins 366MHz (66x5.5) 2.2v |
Socket 370 | 64KB unified (4-way) 256KB on-Die L2 (8-way exclusive) * 4GB cacheable |
22 million 0.18µm process ?mm² die |
(Joshua) February 22, 2000 - {$84} [not released] |
370 pins 400MHz (133x3.0) 2.2v |
Socket 370 | 64KB unified (4-way) 256KB on-Die L2 (8-way exclusive) * 4GB cacheable |
22 million 0.18µm process ?mm² die |
(Joshua) February 22, 2000 - {$99} [not released] |
370 pins 450MHz (100x4.5) 434MHz (124x3.5) 2.2v |
Socket 370 | 64KB unified (4-way) 256KB on-Die L2 (8-way exclusive) * 4GB cacheable |
22 million 0.18µm process ?mm² die |
Cyrix III-500 MMX 3DNow! (Samuel/C5) June 6, 2000 |
370 pins 500MHz (100x5.0) 1.9v or 2.0v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) |
11.3 million 0.18µm process 75mm² die |
Cyrix III-533 MMX 3DNow! (Samuel/C5) June 6, 2000 - {$75} |
370 pins 533MHz (133x4.0) 1.9v or 2.0v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) |
11.3 million 0.18µm process 75mm² die |
Cyrix III-550 MMX 3DNow! (Samuel/C5) June 6, 2000 |
370 pins 550MHz (100x5.5) 1.9v or 2.0v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) |
11.3 million 0.18µm process 75mm² die |
Cyrix III-600 MMX 3DNow! (Samuel/C5) June 6, 2000 |
370 pins 600MHz (100x6.0) 1.9v or 2.0v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) |
11.3 million 0.18µm process 75mm² die |
Cyrix III-650 MMX
3DNow! (Samuel/C5) November 30, 2000 - {$55} |
370 pins 650MHz (100x6.5) 1.9v or 2.0v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) |
11.3 million 0.18µm process 75mm² die |
Cyrix III-667 MMX
3DNow! (Samuel/C5) November 30, 2000 - {$60} |
370 pins 666MHz (133x5.0) 1.9v or 2.0v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) |
11.3 million 0.18µm process 75mm² die |
Cyrix III-700 MMX
3DNow! (Samuel/C5) 2001? |
370 pins 700MHz (100x7.0) 1.9v or 2.0v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) |
11.3 million 0.18µm process 75mm² die |
C3-733A MMX 3DNow! (Samuel 2/C5B) March 25, 2001 - {$54} |
370 pins 733MHz (133x5.5) 1.5v or 1.6v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.2 million 0.15µm process 52mm² die |
C3-750A MMX 3DNow! (Samuel 2/C5B) March 25, 2001 |
370 pins 750MHz (100x7.5) 1.5v or 1.6v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.2 million 0.15µm process 52mm² die |
C3-800A MMX 3DNow! (Samuel 2/C5B) 2001 |
370 pins 800MHz (100x8.0) 1.6v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.2 million 0.15µm process 52mm² die |
(Samuel 2/C5B) [not released] |
370 pins 850MHz (100x8.5) 1.6v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.2 million 0.15µm process 52mm² die |
(Samuel 2/C5B) [not released] |
370 pins 866MHz (133x6.5) 1.6v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.2 million 0.15µm process 52mm² die |
C3-800A MMX
3DNow! (Ezra/C5C) 2001 |
370 pins 800MHz (100x8.0) 800MHz (133x6.0) 1.35v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.4 million 0.13/0.15µm process 52mm² die |
C3-850A MMX
3DNow! (Ezra/C5C) 2001 |
370 pins 850MHz (100x8.5) 1.35v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.4 million 0.13/0.15µm process 52mm² die |
C3-866A MMX 3DNow! (Ezra/C5C) September 11, 2001 |
370 pins 866MHz (133x6.5) 1.35v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.4 million 0.13/0.15µm process 52mm² die |
(Ezra/C5C) [not released] |
370 pins 900MHz (100x9.0) 1.35v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.4 million 0.13/0.15µm process 52mm² die |
(Ezra/C5C) [not released] |
370 pins 933MHz (133x7.0) 1.35v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.4 million 0.13/0.15µm process 52mm² die |
(Ezra/C5C) [not released] |
370 pins 1000MHz (133x7.5) 1.35v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.4 million 0.13/0.15µm process 52mm² die |
C3-800T MMX 3DNow! (Ezra-T/C5M) 3Q 2001 |
370 pins 800MHz (133x6.0) 1.35v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
(Ezra-T/C5M) [not released] |
370 pins 850MHz (100x8.5) 1.35v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
C3-866T MMX 3DNow! (Ezra-T/C5M) 3Q 2001 |
370 pins 866MHz (133x6.5) 1.35v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
(Ezra-T/C5M) [not released] |
370 pins 900MHz (100x9.0) 1.35v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
C3-933T MMX 3DNow! (Ezra-T/C5M) December 19, 2001 |
370 pins 933MHz (133x7.0) 1.35v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.4 million 0.13/0.15µm process 52mm² die |
C3-1.0T MMX 3DNow! (Ezra-T/C5M) June 3, 2002 |
370 pins 1000MHz (133x7.5) 1.35v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
(Ezra-T/C5N) [not released] |
370 pins 900MHz (100x9.0) 1.25v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
(Ezra-T/C5N) [not released] |
370 pins 1000MHz (100x10.0) 1.25v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
(Ezra-T/C5N) [not released] |
370 pins 1100MHz (100x11.0) 1.25v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
(Ezra-T/C5N) [not released] |
370 pins 1200MHz (100x12.0) 1.25v |
Socket 370 1.25v AGTL |
64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (4-way exclusive) * ?GB cacheable |
15.5 million 0.13/0.15µm process 56mm² die |
(Nehemiah/C5X) [not released] |
370 pins 1200MHz (100x12.0) ?v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 256KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process 78mm² die |
(Nehemiah/C5X) [not released] |
370 pins 1300MHz (100x13.0) ?v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 256KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process 78mm² die |
C3-1.0G MMX SSE (Nehemiah/C5XL) January 22, 2003 |
370 pins 1000MHz (100x10.0) 1.4v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process 52mm² die |
(Nehemiah/C5XL) [not released] |
370 pins 1200MHz (100x12.0) ?v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process 52mm² die |
(Nehemiah/C5XL) [not released] |
370 pins 1300MHz (100x13.0) ?v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process 52mm² die |
(Nehemiah/C5XL) [not released] |
370 pins 1400MHz (100x14.0) ?v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process 52mm² die |
(Nehemiah/C5XL) [not released] |
370 pins 1500MHz (100x15.0) ?v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) 64KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process 52mm² die |
(Esther/C5YL) [not released] |
370 pins 2000MHz (?x?) ?v |
Socket 370 | 64KB data (4-way) 64KB instruction (2-way) ?KB on-Die L2 (16-way) * ?GB cacheable |
? million 0.13µm process ?mm² die |
586 Processor Adapters | ||
---|---|---|
Adapter Manufacturer |
Natural State |
Sockets |
CCT 586 Adapter (K5, K6, IBM 6x86) |
296 pins AMD K5: PR100 {100MHz (66x1.5)} AMD K6: 233MHz (66x3.5) 200MHz (66x3.0) 166MHz (66x2.5) IBM 6x86: PR200 {150MHz (75x2.0)} PR166 {133MHz (66x2)} 3.3v to 2.8v/3.3v split 3.3v to 3.2v/3.3v split |
Socket 5 Socket 7 |
Computer Nerd RA3 Adapter (6x86, Pentium) |
296 pins Cyrix 6x86: PR166 {133MHz (66x2.0)} PR150 {120MHz (60x2.0)} Intel P54C: 166MHz (66x2.5) 150MHz (60x2.5) 133MHz (66x2) 120MHz (60x2) 100MHz (60x1.5) 5v to 3.3v |
Socket 4 |
Computer Nerd RA5 Adapter (K6, 6x86L, Pentium MMX) |
296 pins AMD K6: 233MHz (66x3.5) 200MHz (66x3.0) 166MHz (66x2.5) Cyrix 6x86L: PR200 {150MHz (75x2.0)} PR166 {133MHz (66x2.0)} PR150 {120MHz (60x2.0)} PR133 {100MHz (55x2.0)} PR120 {100MHz (50x2.0)} Intel P55C: 233MHz (66x3.5) 200MHz (66x3.0) 166MHz (66x2.5) 3.3v to 2.8v/3.3v split |
Socket 7 |
Concept Manufacturing VA55C Adapter (K6, 6x86L, Pentium MMX) |
296 pins AMD K6: 166MHz (66x2.5) Cyrix 6x86L: PR200 {150MHz (75x2.0)} PR166 {133MHz (66x2)} PR150 {120MHz (60x2)} PR133 {100MHz (55x2.0)} PR120 {100MHz (50x2.0)} Intel P55C: 233MHz (66x3.5) 200MHz (66x3.0) 166MHz (66x2.5) 3.3v to 2.8v/3.3v split |
Socket 5 Socket 7 |
Concept Manufacturing VAK6-2 (AMD K6-2) |
296 pins 333MHz (66x5.0) 300MHz (66x4.5) 266MHz (66x4.0) 3.3v to 2.2v/3.3v split 2.8v to 2.2v/3.3v split 2.9v to 2.2v/3.3v split |
Socket 7 |
Evergreen PR166 (Cyrix 6x86L PR166+) |
296 pins PR166 {133MHz (66x2.0)} 3.3v to 2.8v/3.3v split |
Socket 5 Socket 7 |
Evergreen MxPro (IDT Winchip) |
296 pins 200MHz (66x3.0) 180MHz (60x3.0) 3.3v |
Socket 5 Socket 7 |
Evergreen MxPro-233 (AMD K6 233) |
296 pins 233MHz (66x3.5) 3.3v to 3.2v/3.3v split |
Socket 5 Socket 7 |
Evergreen Spectra (K6-2, Winchip-2) |
296 pins AMD K6-2: 400MHz (66x6.0) 333MHz (66x5.0) IDT Winchip: 233MHz (66x3.5) 3.3v 3.3v to 2.2v/3.3v split |
Socket 5 Socket 7 |
Evergreen Spectra III (Cyrix-III, Celeron, Pentium III) |
370 pins 1000MHz (100x10.0) 900MHz (100x9.0) 850MHz (100x8.5) 766MHz (66x11.5) 600MHz (66x6.0) 550MHz (100x5.5) 1.9v |
Socket 370 |
Evergreen AcceleraPCI (formerly Eclipse PCI) (370-pin Celeron) |
PCI Slot 466MHz (66x7.0) 433MHz (66x6.5) 400MHz (66x6.0) 366MHz (66x5.5) 333MHz (66x5.0) 300MHz (66x4.5) 5v PCI |
Socket 4 Socket 5 Socket 7 Socket 8 |
Evergreen Performa (370-pin Celeron) |
242 pins 700MHz (66x10.5) 600MHz (66x9.0) 500MHz (66x7.5) 400MHz (66x6.0) 1.65v |
Slot 1 |
Evergreen Performa (370-pin Pentium-III) |
242 pins 800MHz (100x8.0) 700MHz (100x7.0) 600MHz (100x6.0) 1.65v |
Slot 1 |
Kingston TurboChip (K6, K6-2, Pentium MMX) |
296 pins AMD K6: 200MHz (66x3.0) AMD K6-2: 333MHz (66x5.0) 366MHz (66x5.5) Intel P55C: 233MHz (66x3.5) 3.3v to 2.2v/3.3v split 3.3v to 2.8v/3.3v split 3.3v to 2.9v/3.3v split |
Socket 5 Socket 7 |
Madex 586004 Adapter (K6, 6x86MX, Pentium MMX) |
296 pins AMD K6: 200MHz (66x3.0) Cyrix 6x86MX: PR200 {166MHz (66x2.5)} Intel P55C: 200MHz (66x3.0) 3.3v 3.3v to 2.5v/3.3v split 3.3v to 2.8v/3.3v split 3.3v to 2.9v/3.3v split 3.3v to 3.2v/3.3v split |
Socket 5 Socket 7 |
Madex 586005 Adapter (K6, 6x86MX, Pentium MMX) |
296 pins AMD K6: 300MHz (66x4.5) 266MHz (66x4.0) 233MHz (66x3.5) Cyrix 6x86MX: PR266 {208MHz (80x2.5)} PR233 {188MHz (75x2.5)} PR200 {166MHz (66x2.5)} PR166 {150MHz (60x2.5)} Intel P55C: 233MHz (66x3.5) 210MHz (60x3.5) 200MHz (66x3.0) 175MHz (50x3.5) 166MHz (66x2.5) 3.3v 3.3v to 2.1v/3.3v split 3.3v to 2.5v/3.3v split 3.3v to 2.8v/3.3v split 3.3v to 2.9v/3.3v split 3.3v to 3.2v/3.3v split |
Socket 5 Socket 7 |
Madex 586006 Adapter (K6-2, K6-III, Pentium MMX) |
296 pins AMD K6-2/K6-III: 400MHz (66x6.0) 366MHz (66x5.5) 333MHz (66x5.0) 300MHz (66x4.5) 266MHz (66x4.0) 233MHz (66x3.5) Intel P55C: 233MHz (66x3.5) 210MHz (60x3.5) 200MHz (66x3.0) 175MHz (50x3.5) 166MHz (66x2.5) 3.3v 3.3v to 2.1v/3.3v split 3.3v to 2.2v/3.3v split 3.3v to 2.4v/3.3v split 3.3v to 2.5v/3.3v split 3.3v to 2.8v/3.3v split 3.3v to 2.9v/3.3v split 3.3v to 3.2v/3.3v split |
Socket 5 Socket 7 |
Madex 586009 Adapter (K6, Pentium MMX) |
296 pins AMD K6: 200MHz (66x3.0) Intel P55C: 233MHz (66x3.5) 3.5v 3.3v 3.3v to 1.8v/3.3v split . . . 3.3v to 3.2v/3.3v split |
Socket 5 Socket 7 |
New Wave NW Slot-T-100 Adapter (Intel Celeron-T) |
242 pins 1400MHz (100x14.0) 1300MHz (100x13.0) 1200MHz (100x12.0) 2.0v |
Slot 1 |
New Wave NW Slot-T-133 Adapter (Intel Pentium III-T (dual)) |
242 pins 1400MHz (133x10.5) 1266MHz (133x9.5) 1133MHz (133x8.5) 2.0v |
Slot 1 |
New Wave NW 370T-100 Adapter (Intel Celeron-T) |
370 pins 1400MHz (100x14.0) 1300MHz (100x13.0) 1200MHz (100x12.0) 1.6v |
Socket 370 |
New Wave NW 370T-133 Adapter (Intel Pentium III-T (dual)) |
370 pins 1400MHz (133x10.5) 1266MHz (133x9.5) 1133MHz (133x8.5) 1.6v |
Socket 370 |
PNY Quickchip-200 (IDT Winchip 200) |
296 pins 200MHz (66x3.0) |
Socket 5 |
PNY Quickchip-3D-200 (IDT Winchip 200) |
296 pins 200MHz (66x3.0) |
Socket 5 Socket 7 |
PowerLeap PL/54C Adapter (Winchip, Pentium) |
273 pins IDT Winchip: 200MHz (66x3.0) 180MHz (60x3.0) Intel P54C: 200MHz (66x3.0) 166MHz (66x2.5) 150MHz (60x2.5) 133MHz (66x2.0) 120MHz (60x2.0) 100MHz (66x1.5) 90MHz (60x1.5) 75MHz (50x1.5) 5v to 3.3v |
Socket 4 |
PowerLeap PL/54C-MMX Adapter (K6, Winchip, Pentium, Pentium MMX) (2.2v K6, K6-2 on Rev. 4) |
273 pins AMD K6/K6-2: 333MHz (66x5.0) 300MHz (66x4.5) 266MHz (66x4.0) 233MHz (66x3.5) 210MHz (60x3.5) 200MHz (66x3.0) 180MHz (60x3.0) 166MHz (66x2.5) 150MHz (60x2.5) IDT Winchip: 266MHz (66x4.0) 240MHz (60x4.0) 200MHz (66x3.0) 180MHz (60x3.0) Intel P54C: 200MHz (66x3.0) 166MHz (66x2.5) 150MHz (60x2.5) 133MHz (66x2.0) 120MHz (60x2.0) 100MHz (66x1.5) 90MHz (60x1.5) 75MHz (50x1.5) Intel P55C: 233MHz (66x3.5) 210MHz (60x3.5) 200MHz (66x3.0) 175MHz (50x3.5) 166MHz (66x2.5) 150MHz (60x2.5) 150MHz (50x3.0) 5v to 2.2v/3.3v split 5v to 2.5v/3.3v split 5v to 2.8v/3.3v split 5v to 2.9v/3.3v split 5v to 3.3v |
Socket 4 |
PowerLeap PL/OD54C Adapter (Intel Pentium) |
296 pins 200MHz (66x3.0) 180MHz (60x3.0) 166MHz (66x2.5) 150MHz (60x2.5) 150MHz (50x3.0) 133MHz (66x2.0) 120MHz (60x2.0) 3.3v |
Socket 5 Socket 7 |
PowerLeap PL/ProMMX Adapter (w/ SVRM) (K6, K6-2, K6-III, 6x86L, 6x86MX Winchip, Pentium, Pentium MMX) |
296 pins AMD K6/K6-2/K6-III: 400MHz (66x6.0) 366MHz (66x5.5) 333MHz (66x5.0) 300MHz (66x4.5) 266MHz (66x4.0) 233MHz (66x3.5) 210MHz (60x3.5) 200MHz (66x3.0) 180MHz (60x3.0) 166MHz (66x2.5) 150MHz (60x2.5) Cyrix 6x86L: PR200+ {150MHz (75x2.0)} PR166+ {133MHz (66x2.0)} PR150+ {120MHz (60x2.0)} PR133+ {110MHz (55x2.0)} Cyrix 6x86MX: PR300 {233MHz (66x3.5)} PR233 {188MHz (75x2.5)} PR200 {166MHz (66x2.5)} PR166 {150MHz (60x2.5)} IDT Winchip: 266MHz (66x4.0) 240MHz (60x4.0) 200MHz (66x3.0) 180MHz (60x3.0) Intel P54C: 200MHz (66x3.0) 166MHz (66x2.5) 150MHz (60x2.5) Intel P55C: 233MHz (66x3.5) 210MHz (60x3.5) 200MHz (66x3.0) 175MHz (50x3.5) 166MHz (66x2.5) 150MHz (60x2.5) 150MHz (50x3.0) 3.3v 3.3v to 1.8v/3.3v split 3.3v to 2.1v/3.3v split 3.3v to 2.2v/3.3v split 3.3v to 2.4v/3.3v split 3.3v to 2.5v/3.3v split 3.3v to 2.8v/3.3v split 3.3v to 2.9v/3.3v split 3.3v to 3.2v/3.3v split |
Socket 7 |
PowerLeap PL/K6-III Adapter (K6, K6-2, K6-III, 6x86L, 6x86MX Winchip, Pentium, Pentium MMX) |
296 pins All PL/Pro-MMX chips plus: AMD K6-III: 450MHz (75x6.0) 400MHz (66x6.0) 3.3v to 2.4v/3.3v split |
Socket 5 Socket 7 |
PowerLeap PL/PII Adapter (Intel Celeron) |
242 pins 500MHz (66x7.5) 466MHz (66x7.0) 433MHz (66x6.5) 400MHz (66x6.0) 366MHz (66x5.5) 333MHz (66x5.0) 300MHz (66x4.5) 2.0v |
Slot 1 |
PowerLeap PL-Pro/II Adapter (Intel Celeron) |
387 pins 533MHz (66x8.0) 500MHz (66x7.5) 466MHz (66x7.0) 433MHz (66x6.5) 400MHz (66x6.0) 366MHz (66x5.5) 333MHz (66x5.0) 300MHz (66x4.5) 2.0v |
Socket 8 |
PowerLeap PL-Renaissance/AT (supports most Socket 7 chips) |
ISA Slot 550MHz (100x5.5) 500MHz (100x5.0) 450MHz (100x4.5) 400MHz (100x4.0) 350MHz (100x3.5) 333MHz (66x5.0) 300MHz (66x4.5) 266MHz (66x4.0) 233MHz (66x3.5) 5v ISA |
any ISA slot |
PowerLeap PL-Renaissance/PCI (supports socketed Celeron and Pentium-III chips) |
PCI Slot 650MHz (100x6.5) 600MHz (100x6.0) 550MHz (100x5.5) 500MHz (100x5.0) 450MHz (100x4.5) 400MHz (100x4.0) 350MHz (100x3.5) 333MHz (66x5.0) 300MHz (66x4.5) 3.3v PCI |
any PCI slot |
PowerLeap PL-Neo S370 Adapter (Intel Pentium III) |
370 pins 866MHz (133x6.5) 850MHz (100x8.5) 800MHz (133x6.0) 800MHz (100x8.0) 750MHz (100x7.5) 733MHz (133x5.5) 700MHz (100x7.0) 666MHz (133x5.0) 650MHz (100x6.5) 600MHz (133x4.5) 600MHz (100x6.0) 550MHz (100x5.5) 533MHz (133x4.0) 500MHz (100x5.0) 1.6v |
Socket 370 |
PowerLeap PL-Renaissance/370S (Intel Celeron and Pentium-III) |
ISA Slot 1.0GHz (133x7.5) 1.0GHz (100x10.0) 950MHz (100x9.5) 933MHz (133x7.0) 900MHz (100x9.0) 866MHz (133x6.5) 850MHz (100x8.5) 800MHz (133x6.0) 800MHz (100x8.0) 750MHz (100x7.5) 733MHz (133x5.5) 700MHz (100x7.0) 700MHz (66x10.5) 666MHz (133x5.0) 666MHz (66x10.0) 650MHz (100x6.5) 633MHz (66x9.5) 600MHz (133x4.5) 600MHz (100x6.0) 600MHz (66x9.0) 566MHz (66x8.5) 550MHz (100x5.5) 533MHz (66x8.0) 500MHz (100x5.0) 500MHz (66x7.5) 466MHz (66x7.0) 450MHz (100x4.5) 433MHz (66x6.5) 400MHz (100x4.0) 400MHz (66x6.0) 366MHz (66x5.5) 350MHz (100x3.5) 333MHz (66x5.0) 300MHz (66x4.5) 266MHz (66x4.0) 233MHz (66x3.5) 5v ISA |
any ISA slot |
PowerLeap PL-iP3 Adapter (Intel Celeron) |
370 pins 900MHz (100x9.0) 850MHz (100x8.5) 800MHz (100x8.0) 750MHz (100x7.5) 700MHz (66x10.5) 633MHz (66x9.5) 533MHz (66x8.0) VRM 8.4 compatible |
Slot 1 |
PowerLeap PL-iP3 Adapter (Intel Pentium III) |
370 pins 1.0B (133x7.5) 1.0GHz (100x10.0) 950MHz (100x9.5) 933MHz (133x7.0) 900MHz (100x9.0) 866MHz (133x6.5) 850MHz (100x8.5) 800MHz (133x6.0) 800MHz (100x8.0) 750MHz (100x7.5) 700MHz (100x7.0) VRM 8.4 compatible |
Slot 1 |
PowerLeap PL-iP3/T Adapter (Intel Celeron, Pentium III) |
370 pins 1.26GHz (133x9.5) 1.2GHz (100x12.0) 1.1GHz (100x11.0) 1.0B (133x7.5) 1.0GHz (100x10.0) 950MHz (100x9.5) 933MHz (133x7.0) 900MHz (100x9.0) 866MHz (133x6.5) 850MHz (100x8.5) 800MHz (133x6.0) 800MHz (100x8.0) 750MHz (100x7.5) 700MHz (100x7.0) VRM 8.5 compatible |
Slot 1 |
Trinity Works P6x Adapter (AMD K5) |
273 pins PR166 {116MHz (66x1.75)} PR133 {100MHz (66x1.5)} PR120 {90MHz (60x1.5)} 5v to 3.52v |
Socket 4 |
Trinity Works P7x Adapter (AMD K5) |
296 pins PR166 {116MHz (66x1.75)} PR133 {100MHz (66x1.5)} 5v to 3.52v |
Socket 5 |
Athlon (Slot A) | ||||
---|---|---|---|---|
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Athlon-500 MMX 3DNow! (K7) August 9, 1999 - {$249} |
575 pins (242 pin SEC) 500MHz (100x5.0) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.25µm process 184mm² die |
Athlon-550 MMX 3DNow! (K7) August 9, 1999 - {$449} |
575 pins (242 pin SEC) 550MHz (100x5.5) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.25µm process 184mm² die |
Athlon-600 MMX 3DNow! (K7) August 9, 1999 - {$615} |
575 pins (242 pin SEC) 600MHz (100x6.0) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.25µm process 184mm² die |
Athlon-650 MMX 3DNow! (K7) August 9, 1999 - {$849} |
575 pins (242 pin SEC) 650MHz (100x6.5) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.25µm process 184mm² die |
Athlon-700 MMX 3DNow! (K7) October 4, 1999 - {$849} |
575 pins (242 pin SEC) 700MHz (100x7.0) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.25µm process 184mm² die |
Athlon-550 MMX 3DNow! (K75) January 2000 |
575 pins (242 pin SEC) 550MHz (100x5.5) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-600 MMX 3DNow! (K75) January 2000 |
575 pins (242 pin SEC) 600MHz (100x6.0) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-650 MMX 3DNow! (K75) January 2000 |
575 pins (242 pin SEC) 650MHz (100x6.5) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-700 MMX 3DNow! (K75) January 2000 |
575 pins (242 pin SEC) 700MHz (100x7.0) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-750 MMX 3DNow! (K75) November 29, 1999 - {$799} |
575 pins (242 pin SEC) 750MHz (100x7.5) (64-bit dual-pumped bus) 1.6v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2.5 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-800 MMX 3DNow! (K75) January 6, 2000 - {$849} |
575 pins (242 pin SEC) 800MHz (100x8.0) (64-bit dual-pumped bus) 1.7v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2.5 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-850 MMX 3DNow! (K75) February 11, 2000 - {$849} |
575 pins (242 pin SEC) 850MHz (100x8.5) (64-bit dual-pumped bus) 1.7v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/2.5 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-900 MMX 3DNow! (K75) March 6, 2000 - {$899} |
575 pins (242 pin SEC) 900MHz (100x9.0) (64-bit dual-pumped bus) 1.8v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/3 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-950 MMX 3DNow! (K75) March 6, 2000 - {$999} |
575 pins (242 pin SEC) 950MHz (100x9.5) (64-bit dual-pumped bus) 1.8v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/3 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-1G MMX 3DNow! (K75) March 6, 2000 - {$1299} |
575 pins (242 pin SEC) 1000MHz (100x10.0) (64-bit dual-pumped bus) 1.8v/3.3v split |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB unified L2 (1/3 speed) (2-way) * 64GB cacheable |
22 million 0.18µm process 102mm² die |
Athlon-650 MMX 3DNow! (Thunderbird) |
? pins (242 pin SEC) 650MHz (100x6.5) (64-bit dual-pumped bus) 1.7v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-700 MMX 3DNow! (Thunderbird) |
? pins (242 pin SEC) 700MHz (100x7.0) (64-bit dual-pumped bus) 1.7v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-750 MMX 3DNow! (Thunderbird) June 5, 2000 - {$319} |
? pins (242 pin SEC) 750MHz (100x7.5) (64-bit dual-pumped bus) 1.7v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-800 MMX 3DNow! (Thunderbird) June 5, 2000 - {$359} |
? pins (242 pin SEC) 800MHz (100x8.0) (64-bit dual-pumped bus) 1.7v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-850 MMX 3DNow! (Thunderbird) June 5, 2000 - {$507} |
? pins (242 pin SEC) 850MHz (100x8.5) (64-bit dual-pumped bus) 1.7v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-900 MMX 3DNow! (Thunderbird) June 5, 2000 - {$589} |
? pins (242 pin SEC) 900MHz (100x9.0) (64-bit dual-pumped bus) 1.75v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-950 MMX 3DNow! (Thunderbird) June 5, 2000 - {$759} |
? pins (242 pin SEC) 950MHz (100x9.5) (64-bit dual-pumped bus) 1.75v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1G MMX 3DNow! (Thunderbird) June 5, 2000 - {$990} |
? pins (242 pin SEC) 1000MHz (100x10.0) (64-bit dual-pumped bus) 1.75v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
(Mustang) [cancelled] |
? pins (242 pin SEC) 1333MHz (133x10) (64-bit dual-pumped bus) ?v |
Slot A | 64KB data (2-way) 64KB instruction (2-way) 512KB or 1MB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
? million 0.18µm process 120+mm² die |
Athlon (Socket A) | ||||
---|---|---|---|---|
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Duron-600 MMX 3DNow! (Spitfire) June 19, 2000 - {$112} |
453 pins 600MHz (100x6.0) (64-bit dual-pumped bus) 1.5v or 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-650 MMX 3DNow! (Spitfire) June 19, 2000 - {$154} |
453 pins 650MHz (100x6.5) (64-bit dual-pumped bus) 1.5v or 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-700 MMX 3DNow! (Spitfire) June 19, 2000 - {$192} |
453 pins 700MHz (100x7.0) (64-bit dual-pumped bus) 1.5v or 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-750 MMX 3DNow! (Spitfire) September 5, 2000 - {$181} |
453 pins 750MHz (100x7.5) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-800 MMX 3DNow! (Spitfire) October 17, 2000 - ($170) |
453 pins 800MHz (100x8.0) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-850 MMX 3DNow! (Spitfire) January 8, 2001 - {$149} |
453 pins 850MHz (100x8.5) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-900 MMX 3DNow! (Spitfire) April 2, 2001 - {$129} |
453 pins 900MHz (100x9.0) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-950 MMX 3DNow! (Spitfire) June 6, 2001 - {$122} |
453 pins 950MHz (100x9.5) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25 million 0.18µm process 100mm² die |
Duron-1.0G MMX 3DNow! SSE (Morgan) August 20, 2001 - {$89} |
453 pins 1000MHz (100x10.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25.2 million 0.18µm process 106mm² die |
Duron-1.1G MMX 3DNow!
SSE (Morgan) October 1, 2001 - {$103} |
453 pins 1100MHz (100x11.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25.2 million 0.18µm process 106mm² die |
Duron-1.2G MMX 3DNow!
SSE (Morgan) November 15, 2001 - {$103} |
453 pins 1200MHz (100x12.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25.2 million 0.18µm process 106mm² die |
Duron-1.3G MMX 3DNow!
SSE (Morgan) January 21, 2002 - {$118} |
453 pins 1300MHz (100x13.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
25.2 million 0.18µm process 106mm² die |
(Appaloosa) [not released] |
453 pins 1333MHz (133x10.0) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) ?KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
? million 0.13µm process ?mm² die |
Duron-1.4G MMX 3DNow!
SSE (Applebred) August 2003 - {$32} |
453 pins 1400MHz (133x10.5) (64-bit dual-pumped bus) 1.5v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
? million 0.13µm process ?mm² die |
Duron-1.6G MMX 3DNow!
SSE (Applebred) August 2003 - {$39} |
453 pins 1600MHz (133x12.0) (64-bit dual-pumped bus) 1.5v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
? million 0.13µm process ?mm² die |
Duron-1.8G MMX 3DNow!
SSE (Applebred) August 2003 - {$47} |
453 pins 1800MHz (133x13.5) (64-bit dual-pumped bus) 1.5v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 64KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
? million 0.13µm process ?mm² die |
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Athlon-650 MMX
3DNow! (Thunderbird) 200x? |
453 pins 650MHz (100x6.5) (64-bit dual-pumped bus) 1.7v or 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-700 MMX
3DNow! (Thunderbird) 200x? |
453 pins 700MHz (100x7.0) (64-bit dual-pumped bus) 1.7v or 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-750 MMX 3DNow! (Thunderbird) June 5, 2000 - {$319} |
453 pins 750MHz (100x7.5) (64-bit dual-pumped bus) 1.7v or 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-800 MMX 3DNow! (Thunderbird) June 5, 2000 - {$359} |
453 pins 800MHz (100x8.0) (64-bit dual-pumped bus) 1.7v or 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-850 MMX 3DNow! (Thunderbird) June 5, 2000 - {$507} |
453 pins 850MHz (100x8.5) (64-bit dual-pumped bus) 1.7v or 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-900 MMX 3DNow! (Thunderbird) June 5, 2000 - {$589} |
453 pins 900MHz (100x9.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-950 MMX 3DNow! (Thunderbird) June 5, 2000 - {$759} |
453 pins 950MHz (100x9.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1G MMX 3DNow! (Thunderbird) June 5, 2000 - {$990} |
453 pins 1000MHz (100x10.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1G MMX
3DNow! (Thunderbird) October 30, 2000 - {$385} |
453 pins 1000MHz (133x7.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.1G MMX
3DNow! (Thunderbird) August 28, 2000 - {$853} |
453 pins 1100MHz (100x11.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.13G MMX
3DNow! (Thunderbird) October 30, 2000 - {$506} |
453 pins 1133MHz (133x8.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.2G MMX
3DNow! (Thunderbird) October 17, 2000 - {$612} |
453 pins 1200MHz (100x12.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.2G MMX
3DNow! (Thunderbird) October 30, 2000 - {$673} |
453 pins 1200MHz (133x9.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.3G MMX
3DNow! (Thunderbird) March 22, 2001 - {$318} |
453 pins 1300MHz (100x13.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.33G MMX
3DNow! (Thunderbird) March 22, 2001 - {$350} |
453 pins 1333MHz (133x10.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.4G MMX 3DNow! (Thunderbird) June 6, 2001 - {$253} |
453 pins 1400MHz (100x14.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
Athlon-1.4G MMX 3DNow! (Thunderbird) June 6, 2001 - {$253} |
453 pins 1400MHz (133x10.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37 million 0.18µm process 120mm² die |
(Mustang) [cancelled] |
453 pins 1333MHz (133x10) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB or 1MB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
? million 0.18µm process 120+mm² die |
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Athlon MP-1.0G MMX 3DNow!
SSE (Palomino) June 5, 2001 - {$215} |
453 pins 1000MHz (133x7.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-1.2G MMX 3DNow!
SSE (Palomino) June 5, 2001 - {$265} |
453 pins 1200MHz (133x9.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-1500+ MMX 3DNow!
SSE (Palomino) October 15, 2001 - {$180} |
453 pins 1333MHz (133x10.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-1600+ MMX 3DNow!
SSE (Palomino) October 15, 2001 - {$210} |
453 pins 1400MHz (133x10.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-1800+ MMX 3DNow!
SSE (Palomino) October 15, 2001 - {$302} |
453 pins 1533MHz (133x11.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-1900+ MMX 3DNow!
SSE (Palomino) December 12, 2001 - {$319} |
453 pins 1600MHz (133x12.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-2000+ MMX 3DNow!
SSE (Palomino) March 13, 2002 - {$415} |
453 pins 1666MHz (133x12.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-2100+ MMX 3DNow!
SSE (Palomino) June 19, 2002 - {$262} |
453 pins 1733MHz (133x13.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon MP-2000+ MMX 3DNow!
SSE (Thoroughbred) August 27, 2002 |
453 pins 1666MHz (133x12.5) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 85mm² die |
Athlon MP-2200+ MMX 3DNow!
SSE (Thoroughbred) August 27, 2002 - {$224} |
453 pins 1800MHz (133x13.5) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 85mm² die |
Athlon MP-2400+ MMX 3DNow!
SSE (Thoroughbred) December 10, 2002 - {$228} |
453 pins 2000MHz (133x15.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 85mm² die |
Athlon MP-2600+ MMX 3DNow!
SSE (Thoroughbred) February 4, 2003 - {$273} |
453 pins 2133MHz (133x16.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 85mm² die |
Athlon MP-2800+ MMX 3DNow! SSE (Barton MP) May 6, 2003 - {$275} |
453 pins 2133MHz (133x16) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Athlon XP-1500+ MMX 3DNow!
SSE (Palomino) October 9, 2001 - {$130} |
453 pins 1333MHz (133x10.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon XP-1600+ MMX 3DNow!
SSE (Palomino) October 9, 2001 - {$160} |
453 pins 1400MHz (133x10.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon XP-1700+ MMX 3DNow!
SSE (Palomino) October 9, 2001 - {$190} |
453 pins 1466MHz (133x11.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon XP-1800+ MMX 3DNow!
SSE (Palomino) October 9, 2001 - {$252} |
453 pins 1533MHz (133x11.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon XP-1900+ MMX 3DNow!
SSE (Palomino) November 5, 2001 - {$269} |
453 pins 1600MHz (133x12.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon XP-2000+ MMX 3DNow!
SSE (Palomino) January 7, 2002 - {$339} |
453 pins 1666MHz (133x12.5) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon XP-2100+ MMX 3DNow!
SSE (Palomino) March 13, 2002 - {$420} |
453 pins 1733MHz (133x13.0) (64-bit dual-pumped bus) 1.75v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.5 million 0.18µm process 128mm² die |
Athlon XP-1600+ MMX 3DNow!
SSE (Thoroughbred) May, 2003 |
453 pins 1400MHz (133x10.5) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 81mm² die 84mm² die (Dec 02) |
Athlon XP-1700+ MMX 3DNow!
SSE (Thoroughbred) June 10, 2002 |
453 pins 1466MHz (133x11.0) (64-bit dual-pumped bus) 1.5v or 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 81mm² die 84mm² die (Dec 02) |
Athlon XP-1800+ MMX 3DNow!
SSE (Thoroughbred) June 10, 2002 |
453 pins 1533MHz (133x11.5) (64-bit dual-pumped bus) 1.5v or 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 81mm² die 84mm² die (Dec 02) |
Athlon XP-1900+ MMX 3DNow!
SSE (Thoroughbred) June 10, 2002 |
453 pins 1600MHz (133x12.0) (64-bit dual-pumped bus) 1.5v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 81mm² die |
Athlon XP-2000+ MMX 3DNow!
SSE (Thoroughbred) June 10, 2002 |
453 pins 1666MHz (133x12.5) (64-bit dual-pumped bus) 1.6v or 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 81mm² die 84mm² die (Dec 02) |
Athlon XP-2100+ MMX 3DNow!
SSE (Thoroughbred) June 10, 2002 |
453 pins 1733MHz (133x13.0) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 81mm² die |
Athlon XP-2200+ MMX 3DNow!
SSE (Thoroughbred) June 10, 2002 - {$241} |
453 pins 1800MHz (133x13.5) (64-bit dual-pumped bus) 1.6v or 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 81mm² die 84mm² die (Dec 02) |
Athlon XP-2400+ MMX 3DNow!
SSE (Thoroughbred) August 21, 2002 - {$193} |
453 pins 2000MHz (133x15.0) (64-bit dual-pumped bus) 1.6v or 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Athlon XP-2600+ MMX 3DNow!
SSE (Thoroughbred) August 21, 2002 - {$297} |
453 pins 2133MHz (133x16.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Athlon XP-2600+ MMX 3DNow!
SSE (Thoroughbred) November, 2002 |
453 pins 2083MHz (166x12.5) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Athlon XP-2700+ MMX 3DNow!
SSE (Thoroughbred) November, 2002 - {$349} |
453 pins 2166MHz (166x13.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Athlon XP-2800+ MMX 3DNow!
SSE (Thoroughbred) November, 2002 - {$397} |
453 pins 2250MHz (166x13.5) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Athlon XP-2000+ MMX 3DNow!
SSE (Thorton) September, 2003 |
453 pins 1666MHz (133x12.5) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-2200+ MMX 3DNow!
SSE (Thorton) September, 2003 |
453 pins 1800MHz (133x13.5) (64-bit dual-pumped bus) 1.6v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-2400+ MMX 3DNow!
SSE (Thorton) September, 2003 |
453 pins 2000MHz (133x15.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-2500+ MMX 3DNow!
SSE (Barton) February 10, 2003 |
453 pins 1833MHz (166x11.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-2600+ MMX 3DNow!
SSE (Barton) May 13, 2003 |
453 pins 1916MHz (166x11.5) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-2800+ MMX 3DNow!
SSE (Barton) February 10, 2003 |
453 pins 2083MHz (166x12.5) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-3000+ MMX 3DNow!
SSE (Barton) February 10, 2003 - {$588} |
453 pins 2166MHz (166x13.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-3000+ MMX 3DNow!
SSE (Barton) May 13, 2003 |
453 pins 2100MHz (200x10.5) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
Athlon XP-3200+ MMX 3DNow!
SSE (Barton) May 13, 2003 - {$464} |
453 pins 2200MHz (200x11.0) (64-bit dual-pumped bus) 1.65v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
54.3 million 0.13µm process 101mm² die |
(Thoroughbred-S) |
453 pins ?MHz (?x?) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) ?KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
? million 0.09µm process 50mm² die |
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Sempron-2200+ MMX 3DNow!
SSE (Thoroughbred) July 28, 2004 - {$39} |
453 pins 1500MHz (166x9.0) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Sempron-2300+ MMX 3DNow!
SSE (Thoroughbred) July 28, 2004 - {$45} |
453 pins 1583MHz (166x9.5) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Sempron-2400+ MMX 3DNow!
SSE (Thoroughbred) July 28, 2004 - {$61} |
453 pins 1666MHz (166x10.0) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Sempron-2500+ MMX 3DNow!
SSE (Thoroughbred) July 28, 2004 - {$74} |
453 pins 1750MHz (166x10.5) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Sempron-2600+ MMX 3DNow!
SSE (Thoroughbred) July 28, 2004 - {$85} |
453 pins 1833MHz (166x11.0) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Sempron-2700+ MMX 3DNow!
SSE (Thoroughbred) August, 2004? |
453 pins 1917MHz (166x11.5) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Sempron-2800+ MMX 3DNow!
SSE (Thoroughbred) July 28, 2004 - {$109} |
453 pins 2000MHz (166x12.0) (64-bit dual-pumped bus) ?v |
Socket A | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * 64GB cacheable |
37.2 million 0.13µm process 84mm² die |
Pentium 4 (Socket 423/478) | ||||
---|---|---|---|---|
Intel Processors |
Natural State |
Sockets | L1/L2/L3 Cache (Associativity) |
Transistors |
Pentium 4-1.3G MMX SSE
SSE2 (Willamette) January 3, 2001 - {$409} |
423 pins 1300MHz (100x13) (64-bit quad-pumped bus) 1.7v or 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.4G MMX SSE
SSE2 (Willamette) November 20, 2000 - {$644} |
423 pins 1400MHz (100x14) (64-bit quad-pumped bus) 1.7v or 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.5G MMX SSE
SSE2 (Willamette) November 20, 2000 - {$819} |
423 pins 1500MHz (100x15) (64-bit quad-pumped bus) 1.7v or 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.6G MMX SSE
SSE2 (Willamette) July 2, 2001 - {$294} |
423 pins 1600MHz (100x16) (64-bit quad-pumped bus) 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.7G MMX SSE
SSE2 (Willamette) April 23, 2001 - {$352} |
423 pins 1700MHz (100x17) (64-bit quad-pumped bus) 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.8G MMX SSE
SSE2 (Willamette) July 2, 2001 - {$562} |
423 pins 1800MHz (100x18) (64-bit quad-pumped bus) 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.9G MMX SSE
SSE2 (Willamette) August 27, 2001 - {$375} |
423 pins 1900MHz (100x19) (64-bit quad-pumped bus) 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-2.0G MMX SSE
SSE2 (Willamette) August 27, 2001 - {$562} |
423 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.75v |
Socket 423 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.4G MMX SSE
SSE2 (Willamette) September 27, 2001 |
478 pins 1400MHz (100x14) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.5G MMX SSE
SSE2 (Willamette) August 27, 2001 |
478 pins 1500MHz (100x15) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.6G MMX SSE
SSE2 (Willamette) August 27, 2001 |
478 pins 1600MHz (100x16) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.7G MMX SSE
SSE2 (Willamette) August 27, 2001 |
478 pins 1700MHz (100x17) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.8G MMX SSE
SSE2 (Willamette) August 27, 2001 |
478 pins 1800MHz (100x18) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.9G MMX SSE
SSE2 (Willamette) August 27, 2001 - {$375} |
478 pins 1900MHz (100x19) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-2.0G MMX SSE
SSE2 (Willamette) August 27, 2001 - {$562} |
478 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Pentium 4-1.6A MMX SSE
SSE2 (Northwood) (Low wattage chip) January 7, 2002 |
478 pins 1600MHz (100x16) (64-bit quad-pumped bus) 1.5v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-1.8A MMX SSE
SSE2 (Northwood) (Low wattage chip) January 7, 2002 |
478 pins 1800MHz (100x18) (64-bit quad-pumped bus) 1.5v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-2.0A MMX SSE
SSE2 (Northwood) (Low wattage chip) January 7, 2002 |
478 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.5v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-1.6A MMX SSE
SSE2 (Northwood) January 7, 2002 |
478 pins 1600MHz (100x16) (64-bit quad-pumped bus) 1.5v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-1.8A MMX SSE
SSE2 (Northwood) January 7, 2002 |
478 pins 1800MHz (100x18) (64-bit quad-pumped bus) 1.5v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-2.0A MMX SSE
SSE2 (Northwood) January 7, 2002 - {$364} |
478 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-2.2G MMX SSE
SSE2 (Northwood) January 7, 2002 - {$562} |
478 pins 2200MHz (100x22) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-2.26G MMX SSE
SSE2 (Northwood) May 5, 2002 - {$423} |
478 pins 2266MHz (133x17) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-2.4G MMX SSE
SSE2 (Northwood) April 2, 2002 - {$562} |
478 pins 2400MHz (100x24) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-2.4B MMX SSE
SSE2 (Northwood) May 5, 2002 - {$562} |
478 pins 2400MHz (133x18) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (Jul 02) |
Pentium 4-2.4C MMX SSE
SSE2 (Northwood) (Jackson Hyperthreading) May 21, 2003 - {$178} |
478 pins 2400MHz (200x12) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525 |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-2.5G MMX SSE
SSE2 (Northwood) August 26, 2002 - {$243} |
478 pins 2500MHz (100x25) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-2.53G MMX SSE
SSE2 (Northwood) May 5, 2002 - {$637} |
478 pins 2533MHz (133x19) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 146mm² die 131mm² die (May 02) |
Pentium 4-2.6G MMX SSE
SSE2 (Northwood) August 26, 2002 - {$401} |
478 pins 2600MHz (100x26) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-2.6C MMX SSE
SSE2 (Northwood) (Jackson Hyperthreading) May 21, 2003 - {$218} |
478 pins 2600MHz (200x13) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525 |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-2.67G MMX SSE
SSE2 (Northwood) August 26, 2002 - {$401} |
478 pins 2666MHz (133x20) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-2.8G MMX SSE
SSE2 (Northwood) August 26, 2002 - {$508} |
478 pins 2800MHz (133x21) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-2.8C MMX SSE
SSE2 (Northwood) (Jackson Hyperthreading) May 21, 2003 - {$278} |
478 pins 2800MHz (200x14) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-3.0C MMX SSE
SSE2 (Northwood) (Jackson Hyperthreading) April 14, 2003 - {$417} |
478 pins 3000MHz (200x15) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525 or 1.55v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-3.06G MMX SSE
SSE2 (Northwood) (Jackson Hyperthreading) November 14, 2002 - {$637} |
478 pins 3066MHz (133x23) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v or 1.55v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-3.2C MMX SSE
SSE2 (Northwood) (Jackson Hyperthreading) June 23, 2003 - {$637} |
478 pins 3200MHz (200x16) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v or 1.55v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-3.4C MMX SSE
SSE2 (Northwood) (Jackson Hyperthreading) February 2, 2004 - {$417} |
478 pins 3200MHz (200x16) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v or 1.55v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Pentium 4-2.4E MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) 2004? |
478 pins 2400MHz (200x12) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-2.8A MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) February 2, 2004 - {$178} |
478 pins 2800MHz (133x21) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-2.8E MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) February 2, 2004 - {$178} |
478 pins 2800MHz (200x14) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-3.0E MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) February 2, 2004 - {$218} |
478 pins 3000MHz (200x15) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-3.2E MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) February 2, 2004 - {$278} |
478 pins 3200MHz (200x16) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-3.4E MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) February 2, 2004 - {$417} |
478 pins 3400MHz (200x17) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-3.6E MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) 2004? |
478 pins 3600MHz (200x18) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-520 MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) June 21, 2004 - {$178} |
775 balls 2800MHz (200x14) (64-bit quad-pumped bus) 1.4v |
Socket T | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-530 MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) June 21, 2004 - {$218} |
775 balls 3000MHz (200x15) (64-bit quad-pumped bus) 1.4v |
Socket T | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-540 MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) June 21, 2004 - {$278} |
775 balls 3200MHz (200x16) (64-bit quad-pumped bus) 1.4v |
Socket T | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-550 MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) June 21, 2004 - {$417} |
775 balls 3400MHz (200x17) (64-bit quad-pumped bus) 1.4v |
Socket T | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-560 MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) June 21, 2004 - {$637} |
775 balls 3600MHz (200x18) (64-bit quad-pumped bus) 1.4v |
Socket T | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-570 MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) 2H 2004? |
775 balls 3800MHz (200x19) (64-bit quad-pumped bus) 1.4v |
Socket T | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Pentium 4-580 MMX SSE SSE2
SSE3 (Prescott) (Jackson Hyperthreading) 2H 2004? |
775 balls 4000MHz (200x20) (64-bit quad-pumped bus) 1.4v |
Socket T | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
(Tejas) (Jackson Hyperthreading) [cancelled] |
775 balls 3600MHz (200x18) (64-bit quad-pumped bus) ?v |
Socket T | 24KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * ?GB cacheable |
? million 0.09µm process ?mm² die |
(Tejas) (Jackson Hyperthreading) [cancelled] |
775 balls ?MHz (266x?) (64-bit quad-pumped bus) ?v |
Socket T | 24KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Pentium 4-??? MMX SSE SSE2
SSE3 (Nehalem) (Jackson Hyperthreading) 2005? |
775 balls ?MHz (200x?) (64-bit quad-pumped bus) ?v |
Socket T | ?KB data (8-way) ?k µops trace instruction (8-way) ?MB on-Die unified L2 (8-way) * ?GB cacheable |
? million 0.065µm process ?mm² die |
Intel Processors |
Natural State |
Sockets | L1/L2/L3 Cache (Associativity) |
Transistors |
Pentium 4 Extreme-3.2G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) November 3, 2003 - {$925} |
478 pins 3200MHz (200x16) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v or 1.55v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Pentium 4 Extreme-3.4G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) February 2, 2004 - {$999} |
478 pins 3400MHz (200x17) (64-bit quad-pumped bus) 1.525v or 1.55v or 1.575v or 1.6v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Pentium 4 Extreme-???G MMX
SSE SSE2 (Gallatin) (Jackson Hyperthreading) 2Q 2004? |
478 pins ?MHz (200x?) (64-bit quad-pumped bus) 1.525v or 1.55v or 1.575v or 1.6v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Pentium 4 Extreme-3.2G MMX
SSE SSE2 (Gallatin) (Jackson Hyperthreading) 2004? |
775 balls 3200MHz (200x16) (64-bit quad-pumped bus) 1.525v or 1.55v or 1.575v or 1.6v |
Socket T | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Pentium 4 Extreme-3.4G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) June 21, 2004 |
775 balls 3400MHz (200x17) (64-bit quad-pumped bus) 1.6v |
Socket T | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Pentium 4 Extreme-3.46G MMX
SSE SSE2 (Gallatin) (Jackson Hyperthreading) 3Q 2004? |
775 balls 3466MHz (266x13) (64-bit quad-pumped bus) 1.525v or 1.55v or 1.575v or 1.6v |
Socket T | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Pentium 4 Extreme-720 MMX
SSE SSE2 SSE3 ( ? ) (Jackson Hyperthreading) 4Q 2004? |
775 balls 3733MHz (266x14) (64-bit quad-pumped bus) ?v |
Socket T | ?KB data (8-way) ?k µops trace instruction (8-way) 2MB on-Die unified L2 (8-way) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Intel Processors |
Natural State |
Sockets | L1/L2/L3 Cache (Associativity) |
Transistors |
Celeron-1.7G MMX SSE
SSE2 (Willamette) May 15, 2002 - {$83} |
478 pins 1700MHz (100x17) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Celeron-1.8G MMX SSE
SSE2 (Willamette) June 12, 2002 - {$103} |
478 pins 1800MHz (100x18) (64-bit quad-pumped bus) 1.75v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Celeron-2.0G MMX SSE
SSE2 (Northwood-128) September 18, 2002 - {$103} |
478 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.1G MMX SSE
SSE2 (Northwood-128) November 20, 2002 - {$89} |
478 pins 2100MHz (100x21) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.2G MMX SSE
SSE2 (Northwood-128) November 20, 2002 - {$103} |
478 pins 2200MHz (100x22) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.3G MMX SSE
SSE2 (Northwood-128) March 31, 2003 - {$117} |
478 pins 2300MHz (100x23) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.4G MMX SSE
SSE2 (Northwood-128) March 31, 2003 - {$127} |
478 pins 2400MHz (100x24) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.5G MMX SSE
SSE2 (Northwood-128) June 25, 2003 - {$89} |
478 pins 2500MHz (100x25) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.6G MMX SSE
SSE2 (Northwood-128) June 25, 2003 - {$103} |
478 pins 2600MHz (100x26) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.7G MMX SSE
SSE2 (Northwood-128) September 24, 2003 - {$104} |
478 pins 2700MHz (100x27) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.8G MMX SSE
SSE2 (Northwood-128) November 5, 2003 - {$117} |
478 pins 2800MHz (100x28) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron-2.9G MMX SSE
SSE2 (Northwood-128) 2004? |
478 pins 2900MHz (100x29) (64-bit quad-pumped bus) 1.475v or 1.5v or 1.525v |
Socket 478 | 8KB data (4-way) 12k µops trace instruction (8-way) 128KB on-Die unified L2 (8-way) * 4GB cacheable |
55 million 0.13µm process 131mm² die |
Celeron D-320 MMX SSE SSE2
SSE3 (Prescott) June 24, 2004 - {$69} |
478 pins 2400MHz (133x18) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Celeron D-325 MMX SSE SSE2
SSE3 (Prescott) June 24, 2004 - {$79} |
478 pins 2533MHz (133x19) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Celeron D-330 MMX SSE SSE2
SSE3 (Prescott) June 24, 2004 - {$89} |
478 pins 2666MHz (133x20) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Celeron D-335 MMX SSE SSE2
SSE3 (Prescott) June 24, 2004 - {$117} |
478 pins 2800MHz (133x21) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Celeron D-340 MMX SSE SSE2
SSE3 (Prescott) 2004? |
478 pins 2933MHz (133x22) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Celeron D-345 MMX SSE SSE2
SSE3 (Prescott) 2004? |
478 pins 3066MHz (133x23) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
Celeron D-350 MMX SSE SSE2
SSE3 (Prescott) 2004? |
478 pins 3200MHz (133x24) (64-bit quad-pumped bus) 1.4v |
Socket 478 | 16KB data (8-way) 16k µops trace instruction (8-way) 256KB on-Die unified L2 (4-way) * 4GB cacheable |
125 million 0.09µm process 112mm² die |
VIA Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
? MMX
SSE (CZA) 2004? |
478 pins ?MHz (?x?) ?v |
Socket 478 | ?KB data (?-way) ?KB instruction (?-way) ?KB on-Die L2 * ?GB cacheable |
? million 0.10µm process ?mm² die |
Xeon (Socket 603) | ||||
---|---|---|---|---|
Intel Processors |
Natural State |
Sockets | L1/L2/L3 Cache (Associativity) |
Transistors |
Xeon-1.4G MMX SSE SSE2 (Foster) May 21, 2001 - {$268} |
603 pins 1400MHz (100x14) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Xeon-1.5G MMX SSE SSE2 (Foster) May 21, 2001 - {$309} |
603 pins 1500MHz (100x15) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Xeon-1.7G MMX SSE SSE2 (Foster) May 21, 2001 - {$406} |
603 pins 1700MHz (100x17) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
Xeon-2.0G MMX SSE SSE2 (Foster) September 25, 2001 - {$615} |
603 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) * 4GB cacheable |
42 million 0.18µm process 217mm² die |
LV Xeon-1.6G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) September 3, 2002 - {$355} |
604 pins 1600MHz (100x16) (64-bit quad-pumped bus) 1.3v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 146mm² die |
Xeon-1.8G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) February 25, 2002 - {$251} |
603 pins 1800MHz (100x18) (64-bit quad-pumped bus) 1.5v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 146mm² die |
Xeon-2.0A MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) February 25, 2002 - {$417} |
603 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.5v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 146mm² die |
LV Xeon-2.0A MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) April, 2003 |
604 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.3v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 146mm² die |
Xeon-2.0B MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) November 18, 2002 - {$198} |
604 pins 2000MHz (133x15) (64-bit quad-pumped bus) 1.5v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 146mm² die |
Xeon-2.2G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) February 25, 2002 - {$615} |
603 pins 2200MHz (100x22) (64-bit quad-pumped bus) 1.5v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 146mm² die |
Xeon-2.4G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) April 23, 2002 - {$615} |
603 pins 2400MHz (100x24) (64-bit quad-pumped bus) 1.5v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 131mm² die |
Xeon-2.4G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) November 18, 2002 - {$234} |
604 pins 2400MHz (133x18) (64-bit quad-pumped bus) 1.5v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 131mm² die |
Xeon-2.6G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) September 11, 2002 - {$433} |
603 pins 2600MHz (100x26) (64-bit quad-pumped bus) 1.5v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 131mm² die |
Xeon-2.67G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) November 19, 2002 - {$337} |
604 pins 2666MHz (133x20) (64-bit quad-pumped bus) 1.5v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 131mm² die |
Xeon-2.8G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) September 11, 2002 - {$562} |
603 pins 2800MHz (100x28) (64-bit quad-pumped bus) 1.5v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 131mm² die |
Xeon-2.8G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) November 18, 2002 - {$455} |
604 pins 2800MHz (133x21) (64-bit quad-pumped bus) 1.5v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 131mm² die |
Xeon-3.06G MMX SSE
SSE2 (Prestonia) (Jackson Hyperthreading) February 3, 2003 - {$722} |
604 pins 3066MHz (133x23) (64-bit quad-pumped bus) 1.5v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) * 64GB cacheable |
55 million 0.13µm process 131mm² die |
Xeon-3.06G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) July 14, 2003 - {$690} |
604 pins 3066MHz (133x23) (64-bit quad-pumped bus) 1.525v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 1MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon-3.2G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) October 6, 2003 - {$851} |
604 pins 3200MHz (133x24) (64-bit quad-pumped bus) 1.525v |
Socket 604 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 1MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon 2.8G MMX SSE SSE2
SSE3 (Nocona) (Jackson Hyperthreading, EM64T) July 28, 2004 - {$209} |
604 pins 2800MHz (200x14) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 64GB cacheable |
125 million 0.09µm process 112mm² die |
Xeon 3.0G MMX SSE SSE2
SSE3 (Nocona) (Jackson Hyperthreading, EM64T) July 28, 2004 - {$316} |
604 pins 3000MHz (200x15) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 64GB cacheable |
125 million 0.09µm process 112mm² die |
Xeon 3.2G MMX SSE SSE2
SSE3 (Nocona) (Jackson Hyperthreading, EM64T) July 28, 2004 - {$455} |
604 pins 3200MHz (200x16) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 64GB cacheable |
125 million 0.09µm process 112mm² die |
Xeon 3.4G MMX SSE SSE2
SSE3 (Nocona) (Jackson Hyperthreading, EM64T) July 28, 2004 - {$690} |
604 pins 3400MHz (200x17) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 64GB cacheable |
125 million 0.09µm process 112mm² die |
Xeon 3.6G MMX SSE SSE2
SSE3 (Nocona) (Jackson Hyperthreading, EM64T) July 28, 2004 - {$851} |
604 pins 3600MHz (200x18) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 64GB cacheable |
125 million 0.09µm process 112mm² die |
Xeon 3.8G MMX SSE SSE2
SSE3 (Nocona) (Jackson Hyperthreading, EM64T) 2004? |
604 pins 3800MHz (200x19) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 64GB cacheable |
125 million 0.09µm process 112mm² die |
Xeon 4.0G MMX SSE SSE2
SSE3 (Nocona) (Jackson Hyperthreading, EM64T) 1Q 2005? |
604 pins 4000MHz (200x20) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 1MB on-Die unified L2 (8-way) * 64GB cacheable |
125 million 0.09µm process 112mm² die |
Xeon ? MMX SSE SSE2
SSE3 (Irwindale) (Jackson Hyperthreading, EM64T) 2004? |
604 pins 3800MHz (200x19) (64-bit quad-pumped bus) 1.4v |
Socket 604 | 16KB data (8-way) 16k µops trace instruction (8-way) 2MB on-Die unified L2 (8-way) * 64GB cacheable |
? million 0.09µm process ?mm² die |
(Jayhawk) (Jackson Hyperthreading) [cancelled] |
? pins ?MHz (166x?) (64-bit quad-pumped bus) ?v |
Socket ? | 24KB data (?-way) 16k µops trace instruction (8-way) ?MB on-Die unified L2 (8-way) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Intel Processors |
Natural State |
Sockets | L1/L2/L3 Cache (Associativity) |
Transistors |
Xeon MP-1.4G MMX SSE SSE2 (Foster MP) (Jackson Hyperthreading) March 12, 2002 - {$1177} |
603 pins 1400MHz (100x14) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) 512KB L3 (?-way) * 64GB cacheable |
108 million 0.18µm process ?mm² die |
Xeon MP-1.5G MMX SSE SSE2 (Foster MP) (Jackson Hyperthreading) March 12, 2002 - {$1980} |
603 pins 1500MHz (100x15) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) 512KB L3 (?-way) * 64GB cacheable |
108 million 0.18µm process ?mm² die |
Xeon MP-1.6G MMX SSE SSE2 (Foster MP) (Jackson Hyperthreading) March 12, 2002 - {$3692} |
603 pins 1600MHz (100x16) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) 1MB L3 (?-way) * 64GB cacheable |
108 million 0.18µm process ?mm² die |
(Foster MP) (Jackson Hyperthreading) [not released] |
603 pins 1700MHz (100x17) (64-bit quad-pumped bus) 1.7v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 256KB on-Die unified L2 (8-way) 1MB L3 (?-way) * 64GB cacheable |
108 million 0.18µm process ?mm² die |
Xeon MP-1.5G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) November 4, 2002 - {$1177} |
603 pins 1500MHz (100x15) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 1MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon MP-1.9G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) November 4, 2002 - {$1980} |
603 pins 1900MHz (100x19) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 1MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon MP-2.0G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) June 30, 2003 - {$1177} |
603 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 1MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon MP-2.0G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) November 4, 2002 - {$3692} |
603 pins 2000MHz (100x20) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon MP-2.2G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) March 2, 2004 - {$1177} |
603 pins 2200MHz (100x22) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ?mm² die |
Xeon MP-2.5G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) June 30, 2003 - {$1980} |
603 pins 2500MHz (100x25) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 1MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon MP-2.7G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) March 2, 2004 - {$1980} |
603 pins 2700MHz (100x27) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ?mm² die |
Xeon MP-2.8G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) June 30, 2003 - {$3692} |
603 pins 2800MHz (100x28) (64-bit quad-pumped bus) 1.475v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 2MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ~230mm² die |
Xeon MP-3.0G MMX SSE
SSE2 (Gallatin) (Jackson Hyperthreading) March 2, 2004 - {$3692} |
603 pins 3000MHz (100x30) (64-bit quad-pumped bus) 1.5v |
Socket 603 | 8KB data (4-way) 12k µops trace instruction (8-way) 512KB on-Die unified L2 (8-way) 4MB on-Die L3 (8-way) * 64GB cacheable |
169 million 0.13µm process ?mm² die |
Xeon MP ? MMX SSE SSE2
SSE3 (Potomac) (Jackson Hyperthreading, Yamhill 64-bit) 2004? |
? pins ?MHz (166x?) (64-bit quad-pumped bus) ?v |
Socket ? | 24KB data (?-way) 16k µops trace instruction (8-way) ?MB on-Die unified L2 (8-way) >4MB on-Die L3 (8-way) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Xeon MP ? MMX SSE SSE2
SSE3 (Tulsa) (Jackson Hyperthreading, dual core) 2005? |
? pins ?MHz (166x?) (64-bit quad-pumped bus) ?v |
Socket ? | 24KB data (?-way) 16k µops trace instruction (8-way) ?MB on-Die unified L2 (8-way) ?MB on-Die L3 (?-way) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Itanium (Merced) | ||||
---|---|---|---|---|
Intel Processors |
Natural State |
Sockets | L1/L2/L3 Cache (Associativity) |
Transistors |
Itanium-733 MMX SSE (Merced) July, 2001 |
418 pins 733MHz (133x5.5) (64-bit dual-pumped bus) ?v |
PAC418 | 16KB data (4-way) 16KB instruction (4-way) 96KB on-Die unified L2 (6-way) 2MB or 4MB unified L3 (4-way) * 16TB cacheable |
25 million 0.18µm process ~300mm² die ? million L3 {?µm - ?mm²} (2MB) 295 million L3 {?µm - ?mm²} (4MB) |
Itanium-800 MMX SSE (Merced) July, 2001 |
418 pins 800MHz (133x6.0) (64-bit dual-pumped bus) ?v |
PAC418 | 16KB data (4-way) 16KB instruction (4-way) 96KB on-Die unified L2 (6-way) 2MB or 4MB unified L3 (4-way) * 16TB cacheable |
25 million 0.18µm process ~300mm² die ? million L3 {?µm - ?mm²} (2MB) 295 million L3 {?µm - ?mm²} (4MB) |
Itanium 2-900 MMX SSE (McKinley) July 8, 2002 - {$1338} (1.5MB) |
611 pins 900MHz (200x4.5) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 1.5MB on-Die unified L3 * ?GB cacheable |
221 million 0.18µm process 463mm² die |
Itanium 2-1.0G MMX SSE (McKinley) July 8, 2002 - {$?} (1.5MB) July 8, 2002 - {$4226} (3MB) |
611 pins 1000MHz (200x5.0) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 1.5MB or 3MB on-Die unified L3 * ?GB cacheable |
221 million 0.18µm process 463mm² die |
Itanium 2-1.3G MMX SSE (Madison) - copper chip June 30, 2003 - {$1338} |
611 pins 1300MHz (200x6.5) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 3MB on-Die unified L3 * ?GB cacheable |
~500 million 0.13µm process ?mm² die |
Itanium 2-1.4G MMX SSE (Madison) - copper chip June 30, 2003 - {$2247} |
611 pins 1400MHz (200x7.0) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 4MB on-Die unified L3 * ?GB cacheable |
~500 million 0.13µm process ?mm² die |
Itanium 2-1.5G MMX SSE (Madison) - copper chip June 30, 2003 - {$3692} |
611 pins 1500MHz (200x7.5) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 6MB on-Die unified L3 * ?GB cacheable |
~500 million 0.13µm process ?mm² die |
LV Itanium 2-1.0G MMX
SSE (Deerfield) September 8, 2003 - {$744} |
611 pins 1000MHz (200x5.0) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 1.5MB on-Die unified L3 * ?GB cacheable |
? million 0.13µm process ?mm² die |
Itanium 2-1.4G MMX
SSE (Deerfield) September 8, 2003 - {$1172} (1.5MB) April 13, 2004 - {$1172} (3MB) |
611 pins 1400MHz (200x7.0) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 1.5MB or 3MB on-Die unified L3 * ?GB cacheable |
? million 0.13µm process ?mm² die |
Itanium 2-1.6G MMX
SSE (Deerfield) May, 2004 - {$2408} |
611 pins 1600MHz (200x8.0) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 3MB on-Die unified L3 * ?GB cacheable |
? million 0.13µm process ?mm² die |
Itanium 2 MMX
SSE (Deerfield) 2004? |
611 pins ?MHz (200x?) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 3MB on-Die unified L3 * ?GB cacheable |
? million 0.13µm process ?mm² die |
Itanium 2 MMX
SSE (Madison 9M) 2004? |
611 pins ?MHz (200x?) (128-bit dual-pumped bus) ?v |
PAC611 | 16KB data 16KB instruction 256KB on-Die unified L2 3MB on-Die unified L3 * ?GB cacheable |
? million ?µm process ?mm² die |
Itanium 2 MMX
SSE (Montecito) (Jackson Hyperthreading, dual core) 2005? |
611 pins ?MHz (?x?) (128-bit dual-pumped bus) ?v |
PAC611 | ?KB data ?KB instruction ?KB on-Die unified L2 24MB on-Die unified L3 * ?GB cacheable |
? million 0.09µm process ?mm² die |
Itanium 2 MMX
SSE (Fanwood - 2-way) (Jackson Hyperthreading, dual core) 2006? |
? pins ?MHz (?x?) (128-bit dual-pumped bus) ?v |
? | ?KB data ?KB instruction ?KB on-Die unified L2 ?MB on-Die unified L3 * ?GB cacheable |
? million ?µm process ?mm² die |
Itanium 2 MMX
SSE (Millington - 2-way) (Jackson Hyperthreading, dual core) 2006? |
? pins ?MHz (?x?) (128-bit dual-pumped bus) ?v |
? | ?KB data ?KB instruction ?KB on-Die unified L2 ?MB on-Die unified L3 * ?GB cacheable |
? million ?µm process ?mm² die |
Itanium 2 MMX
SSE (Shavano) (Jackson Hyperthreading) 2005? |
? pins ?MHz (?x?) (128-bit dual-pumped bus) ?v |
? | ?KB data ?KB instruction ?KB on-Die unified L2 ?MB on-Die unified L3 * ?GB cacheable |
? million ?µm process ?mm² die |
Itanium 2 MMX
SSE (Montvale) (Jackson Hyperthreading, dual core) 2006? |
? pins ?MHz (?x?) (128-bit dual-pumped bus) ?v |
? | ?KB data ?KB instruction ?KB on-Die unified L2 24MB on-Die unified L3 * ?GB cacheable |
? million ?µm process ?mm² die |
Itanium 2 MMX
SSE (Tukwila) (Jackson Hyperthreading, dual core) 2006? |
? pins ?MHz (?x?) (?-bit ?-pumped bus) ?v |
? | ?KB data ?KB instruction ?KB on-Die unified L2 ?MB on-Die unified L3 * ?GB cacheable |
? million 0.65µm process ?mm² die |
Itanium 2 MMX
SSE (Dimona) (Jackson Hyperthreading, dual core) 2006? |
? pins ?MHz (?x?) (?-bit ?-pumped bus) ?v |
? | ?KB data ?KB instruction ?KB on-Die unified L2 ?MB on-Die unified L3 * ?GB cacheable |
? million ?µm process ?mm² die |
Athlon 64 - Socket 754 | ||||
---|---|---|---|---|
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
(Clawhammer) (64-bit on-Die unbuffered DDR PC2700 mem controller; 4GB max) |
754 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.13µm process 104mm² die |
Athlon 64-2800+ MMX 3DNow! SSE
SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) March 30, 2004 - {$178} |
754 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64-3000+ MMX 3DNow! SSE
SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) December 15, 2003 - {$218} |
754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64-3200+ MMX 3DNow! SSE
SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) September 23, 2003 - {$417} |
754 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64-3400+ MMX 3DNow! SSE
SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) January 6, 2004 - {$417} |
754 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64-3700+ MMX 3DNow! SSE
SSE2 (Clawhammer) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) June 1, 2004 - {$710} |
754 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64-2800+ MMX 3DNow!
SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) 2004? |
754 pins 1800MHz (200x9.0) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-3000+ MMX 3DNow!
SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) 2004? |
754 pins 2000MHz (200x10.0) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-3200+ MMX 3DNow!
SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) 2004? |
754 pins 2200MHz (200x11.0) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-3400+ MMX 3DNow!
SSE SSE2 (Newcastle) (64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) 2004? |
754 pins 2400MHz (200x12.0) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Sempron-3100+ MMX 3DNow! SSE
SSE2 (Paris) (32-bit; 64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) July 28, 2004 - {$126} |
754 pins 1800MHz (200x9.0) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.13µm process ?mm² die |
Sempron-??? MMX 3DNow! SSE
SSE2 (Paris) (32-bit; 64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max) 2004? |
754 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 754 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.13µm process ?mm² die |
Athlon 64 - Socket 939/940 | ||||
---|---|---|---|---|
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Athlon 64-2800+ MMX 3DNow!
SSE SSE2 (Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 2004? |
939 pins 1800MHz (200x9) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-3000+ MMX 3DNow!
SSE SSE2 (Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 2004? |
939 pins 2000MHz (200x10) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-3500+ MMX 3DNow! SSE
SSE2 (Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) June 1, 2004 - {$500} |
939 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-3800+ MMX 3DNow! SSE
SSE2 (Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) June 1, 2004 - {$720} |
939 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-4000+ MMX 3DNow!
SSE SSE2 (Newcastle) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 4Q 2004? |
939 pins 2600MHz (200x13) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
68.5 million 0.13µm process 144mm² die |
Athlon 64-??? MMX 3DNow! SSE
SSE2 (Victoria) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 2004? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 256KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Athlon 64-4200+ MMX 3DNow!
SSE SSE2 (Winchester) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 1Q 2005? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process 102mm² die |
Athlon 64-4400+ MMX 3DNow!
SSE SSE2 (Winchester) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 2Q 2005? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process 102mm² die |
Athlon 64-??? MMX 3DNow! SSE
SSE2 (Winchester) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 2005? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process 102mm² die |
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Sempron-??? MMX 3DNow! SSE
SSE2 (Palermo) (128-bit on-Die unbuffered DDR-II mem controller) 2005? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Athlon 64 FX-51 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC3200 mem controller; 8GB max) September 23, 2003 - {$733} |
940 pins 2200MHz (200x11) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64 FX-53 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC3200 mem controller; 8GB max) March 18, 2004 - {$733} |
940 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64 FX-53 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) June 1, 2004 - {$799} |
939 pins 2400MHz (200x12) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64 FX-55 MMX 3DNow!
SSE SSE2 (Sledgehammer) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 4Q 2004? |
939 pins 2600MHz (200x13) (64-bit dual-pumped bus) ?v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Athlon 64-FX-57 MMX 3DNow!
SSE SSE2 (San Diego) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 2Q 2005? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ~120mm² die |
Athlon 64-FX-??? MMX 3DNow!
SSE SSE2 (San Diego) (128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max) 2005? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ~120mm² die |
Athlon 64-FX-??? MMX 3DNow!
SSE SSE2 (Toledo) (128-bit on-Die unbuffered DDR-II mem controller) (dual core) 2H 2005? |
939 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.5v |
Socket 939 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Opteron | ||||
---|---|---|---|---|
AMD Processors |
Natural State |
Sockets | L1/L2 Cache (Associativity) |
Transistors |
Opteron-??? MMX 3DNow! SSE
SSE2 (Clawhammer DP) (128-bit on-Die DDR PC2700 mem controller; 8GB max) 2004? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 512KB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.13µm process 104mm² die |
Opteron-140 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) June 30, 2003 - {$229} |
940 pins 1400MHz (200x7.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-142 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) June 30, 2003 - {$438} |
940 pins 1600MHz (200x8.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-144 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) June 30, 2003 - {$669} |
940 pins 1800MHz (200x9.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-146 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) September 9, 2003 - {$669} |
940 pins 2000MHz (200x10.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-146 HE MMX 3DNow!
SSE SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2004? |
940 pins 2000MHz (200x10.0) (64-bit dual-pumped bus) ?v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-146 EE MMX 3DNow!
SSE SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2004? |
940 pins 2000MHz (200x10.0) (64-bit dual-pumped bus) ?v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-148 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) November 17, 2003 - {$733} |
940 pins 2200MHz (200x11.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-150 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) May 18, 2004 - {$637} |
940 pins 2400MHz (200x12.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-240 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) April 22, 2003 - {$283} |
940 pins 1400MHz (200x7.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-242 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) April 22, 2003 - {$690} |
940 pins 1600MHz (200x8.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-244 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) April 22, 2003 - {$794} |
940 pins 1800MHz (200x9.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-246 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) August 5, 2003 - {$794} |
940 pins 2000MHz (200x10.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-246 HE MMX 3DNow!
SSE SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2004? |
940 pins 2000MHz (200x10) (64-bit dual-pumped bus) ?v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-246 EE MMX 3DNow!
SSE SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2004? |
940 pins 2000MHz (200x10) (64-bit dual-pumped bus) ?v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-248 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) November 17, 2003 - {$913} |
940 pins 2200MHz (200x11.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-250 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) May 18, 2004 - {$851} |
940 pins 2400MHz (200x12.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-2XX MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2003? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-840 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) June 30, 2003 - {$749} |
940 pins 1400MHz (200x7.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-842 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) June 30, 2003 - {$1299} |
940 pins 1600MHz (200x8.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-844 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) June 30, 2003 - {$2149} |
940 pins 1800MHz (200x9.0) (64-bit dual-pumped bus) 1.5v or 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-846 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) September 9, 2003 - {$3199} |
940 pins 2000MHz (200x10.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-846 HE MMX 3DNow!
SSE SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2004? |
940 pins 2000MHz (200x10) (64-bit dual-pumped bus) ?v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-846 EE MMX 3DNow!
SSE SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2004? |
940 pins 2000MHz (200x10) (64-bit dual-pumped bus) ?v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-848 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) November 17, 2003 - {$3199} |
940 pins 2200MHz (200x11.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-850 MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) May 18, 2004 - {$1514} |
940 pins 2400MHz (200x12.0) (64-bit dual-pumped bus) 1.5v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-8XX MMX 3DNow! SSE
SSE2 (Sledgehammer) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2004? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) 1.55v |
Socket 940 | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
106 million 0.13µm process 193mm² die |
Opteron-1XX MMX 3DNow! SSE
SSE2 (Venus) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2H 2004? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket ? | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Opteron-2XX MMX 3DNow! SSE
SSE2 (Troy) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2H 2004? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket ? | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Opteron-8XX MMX 3DNow! SSE
SSE2 (Athens) (128-bit on-Die registered DDR PC2700 mem controller; 8GB max) 2H 2004? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket ? | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Opteron-1XX MMX 3DNow! SSE
SSE2 (Denmark) (128-bit on-Die registered DDR-II mem controller) (dual core) 2H 2005? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket ? | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Opteron-2XX MMX 3DNow! SSE
SSE2 (Italy) (128-bit on-Die registered DDR-II mem controller) (dual core) 2H 2005? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket ? | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
Opteron-8XX MMX 3DNow! SSE
SSE2 (Egypt) (128-bit on-Die registered DDR-II mem controller) (dual core) 2H 2005? |
940 pins ?MHz (200x?) (64-bit dual-pumped bus) ?v |
Socket ? | 64KB data (2-way) 64KB instruction (2-way) 1MB on-Die unified L2 (16-way exclusive) * ?GB cacheable |
? million 0.09µm process ?mm² die |
MD - Minimum Delay
(modified timing). Split - Split voltages (lower core with a 3.3v I/O). STD - 3.3v (3.135v ~ 3.465v) - Standard Voltage. VR - 3.38v (3.300v ~ 3.465v) - Voltage Regulated. VRE - 3.52v (3.450v ~ 3.600v) - (B-step) Voltage Regulated Extended. VRE - 3.5v (3.400v ~ 3.600v) - (C2 step and later) Voltage Regulated Extended. VRT - 2.9vcore / 3.3vI/O - split Voltage Reduction Technology (mobile chips only). |
Notes:
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